AN1154 STMicroelectronics, AN1154 Datasheet - Page 57

• Manufacturer Part Number: AN1154
• Description: 8031-PSD DESIGN TUTORIAL
• Manufacturer: STMicroelectronics

begin_cycle node istype ’reg’;"This signal takes the state machine out of idle
STATE1..STATE0 node istype ’reg’;"State machine bits
Desired_Level3..Desired_Level0 node istype ’reg’;"The desired gain level
fs7..fs0 node;"Main Flash memory segments
ees3..ees0node;
// Reserved node names
rs0
csiop
jtagsel
pgr1..pgr0
// The following page register bit definitions are an example of how to manipulate
memory to
// facilitate ISP. This scheme is explained in Appendix F of Application note 57.
swapnode 117;" This page register bit (pgr7) will be used for swapping
enable_data_half node 116;
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DLEVEL = [Desired_Level3..Desired_Level0];"Desired gain level set by MCU
MLEVEL = [Measured_Level3..Measured_Level0];"Measured gain level latched by IMCs
STATE_MACHINE = [STATE1..STATE0];
X = .x.;"Don’t care symbol
C = .c.;"Clock symbol
page = [pgr1,pgr0];
address = [a15..a0];"De-muxed microcontroller address signals
node;"Select for the SRAM memory space
node 102;"This is the JTAG enable product term. It is used to enable
" memory segments after a firmware download from the 8031
" UART port has completed. When swap = 0, the secondary
" NVM occupies boot area for ISP, swap = 1, primary NVM
" occupies boot area.
" This page register bit (pgr6) will be used to manipulate
" the EEPROM. The use of this bit is one way to divide the
" EEPROM in into two equal sections, one for boot and one for
" general data. When this bit=0, the boot section is active.
" When this bit = 1, the data section is active.
node;
"the JTAG port signals.
node;"Internal PSD Page Register bits
"EEPROM memory segments
"Control register
DEFINITIONS
AN1154 - APPLICATION NOTE
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