FDC37B77X SMSC Corporation, FDC37B77X Datasheet - Page 112

• Manufacturer Part Number: FDC37B77X
• Description: ENHANCED SUPER I/O CONTROLLER WITH WAKE UP FEATURES
• Manufacturer: SMSC Corporation

SERIAL IRQ
The SMI is enabled onto the SMI frame of the Serial IRQ via bit 6 of SMI Enable Register 2.
SERIAL INTERRUPTS
The FDC37B77x will support the serial interrupt to transmit interrupt information to the host system.
The serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0.
Timing Diagrams For IRQSER Cycle
PCICLK
IRQSER
Drive Source
A) Start Frame timing with source sampled a low pulse on IRQ1
PCICLK = 33Mhz_IN pin
IRQSER = SIRQ pin
1) Start Frame pulse can be 4-8 clocks wide.
IRQ1
SL
or
H
H=Host Control
SL=Slave Control
START
Host Controller
START FRAME
H
1
S=Sample
R
112
T
R=Recovery
T=Turn-around
IRQ0 FRAME IRQ1 FRAME
S
None
R
T
S
IRQ1
R
T
IRQ2 FRAME
S
None
R
T