FDC37B77X SMSC Corporation, FDC37B77X Datasheet - Page 85

• Manufacturer Part Number: FDC37B77X
• Description: ENHANCED SUPER I/O CONTROLLER WITH WAKE UP FEATURES
• Manufacturer: SMSC Corporation

EPP DATA PORT 2
ADDRESS OFFSET = 06H
The EPP Data Port 2 is located at an offset of
'06H' from the base address.
DATA PORT 0 for a description of operation.
This register is only available in EPP mode.
EPP DATA PORT 3
ADDRESS OFFSET = 07H
The EPP Data Port 3 is located at an offset of
'07H' from the base address.
DATA PORT 0 for a description of operation.
This register is only available in EPP mode.
EPP 1.9 OPERATION
When the EPP mode is selected in the
configuration register, the standard and bi-
directional modes are also available. If no EPP
Refer to EPP
Refer to EPP
85
Read, Write or Address cycle is currently
executing, then the PDx bus is in the standard or
bi-directional mode, and all output signals
(STROBE, AUTOFD, INIT) are as set by the
SPP Control Port and direction is controlled by
PCD of the Control port.
In EPP mode, the system timing is closely
coupled to the EPP timing. For this reason, a
watchdog timer is required to prevent system
lockup. The timer indicates if more than 10usec
have elapsed from the start of the EPP cycle
(nIOR or nIOW asserted) to nWAIT being
deasserted (after command).
occurs, the current EPP cycle is aborted and the
time-out condition is indicated in Status bit 0.
During an EPP cycle, if STROBE is active, it
overrides the EPP write signal forcing the PDx
bus to always be in a write mode and the
nWRITE signal to always be asserted.
If a time-out