FDC37B77X SMSC Corporation, FDC37B77X Datasheet - Page 129

• Manufacturer Part Number: FDC37B77X
• Description: ENHANCED SUPER I/O CONTROLLER WITH WAKE UP FEATURES
• Manufacturer: SMSC Corporation

The FDC37B77x implements a group nSMI
output pin. The System Management Interrupt
is a non-maskable interrupt with the highest
priority
management. The nSMI group interrupt output
consists of the enabled interrupts from each of
the functional blocks in the chip. The interrupts
are enabled onto the group nSMI output via the
SMI Enable Registers 1 and 2. The nSMI output
is then enabled onto the group nSMI output pin
via bit[7] in the SMI Enable Register 2.
The logic equation for the nSMI output is as
follows:
nSMI
REGISTERS
The following registers can be accessed when in
configuration
Registers B4-B7 and when not in configuration
they can be accessed through the Index and
Data Register (refer to Table 49B).
SMI Enable Registers
SMI Enable Register 1
(Configuration Register B4, Logical Device 8)
This register is used to enable the different
interrupt sources onto the group nSMI output.
SMI Enable Register 2
(Configuration Register B5, Logical Device 8)
=
(EN_U2INT
(EN_U1INT
(EN_FINT
(EN_WDT
(EN_MINT
(EN_KINT
(EN_IRINT and IRQ_IRINT)
level
(EN_PINT
mode
used
and
and
and
and
at
for
and
and
SYSTEM MANAGEMENT INTERRUPT (SMI)
and
Logical
transparent
IRQ_U2INT)
IRQ_U1INT)
IRQ_WDT)
IRQ_MINT)
IRQ_FINT)
IRQ_KINT)
IRQ_PINT)
Device
power
or
or
or
or
or
or
or
8,
129
This register is used to enable additional
interrupt sources onto the group nSMI output.
This register is also used to enable the group
nSMI output onto the nSMI Serial/Parallel IRQ
pin and the routing of 8042 P12 internally to
nSMI.
SMI Status Registers
SMI Status Register 1
(Configuration Register B6, Logical Device 8)
This register is used to read the status of the
SMI input events. Note: The status bit gets set
whether or not the interrupt is enabled onto the
group SMI output.
SMI Status Register 2
(Configuration Register B7, Logical Device 8)
PME SUPPORT
The FDC37B77x offers support for PCI power
management
management event is requested by a PCI
function via the assertion of the nPME signal.
The assertion and deassertion of nPME is
asynchronous to the PCI clock.
FDC37B77x, only active transitions on the ring
indicator inputs nRI1 and nRI2, valid NEC
infrared remote control frames, active keyboard-
clock edges and active mouse-clock edges can
assert the nPME signal. Note: The keyboard-
data and mouse-data pins are inactive (tri-state)
when V
nPME
configuration registers in logical device number
eight.
LD8:CRC5.0, globally controls PME Wake-up
events. When PME_En is inactive, the nPME
signal can not be asserted. When PME_En is
asserted, any wake source whose individual
CC
functionality
= 0V and V
The
events
PME
TR
is
= 5V
Enable
(PMEs).
controlled
bit,
A
PME_En,
by
In the
power
the