FDC37B77X SMSC Corporation, FDC37B77X Datasheet - Page 154

• Manufacturer Part Number: FDC37B77X
• Description: ENHANCED SUPER I/O CONTROLLER WITH WAKE UP FEATURES
• Manufacturer: SMSC Corporation

Floppy Data Rate
Select Shadow
UART1 FIFO
Control Shadow
UART2 FIFO
Control Shadow
PME Control
Default = 0x00 on
V
PME Status
Default = 0x00 on
POR V
TR
POR
NAME
TR
Table 64 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08]
(R/w Clear)
INDEX
(R/W)
0xC2
0xC3
0xC4
0xC5
0xC6
REG
(R)
Force Change 0 is cleared on nSTEP and nDS0
DSKCHG (FDC DIR Register, Bit 7) = (nDS0 AND
Force Change 0) OR nDSKCHG
Bit[0] Data Rate Select 0
Bit[1] Data Rate Select 1
Bit[2] PRECOMP 0
Bit[3] PRECOMP 1
Bit[4] PRECOMP 2
Bit[5] Reserved
Bit[6] Power Down
Bit[7] Soft Reset
Bit[0] FIFO Enable
Bit[1] RCVR FIFO Reset
Bit[2] XMIT FIFO Reset
Bit[3] DMA Mode Select
Bit[5:4] Reserved
Bit[6] RCVR Trigger (LSB)
Bit[7] RCVR Trigger (MSB)
Bit[0] FIFO Enable
Bit[1] RCVR FIFO Reset
Bit[2] XMIT FIFO Reset
Bit[3] DMA Mode Select
Bit[5:4] Reserved
Bit[6] RCVR Trigger (LSB)
Bit[7] RCVR Trigger (MSB)
Bit[0] PME_En
= 0
= 1
Bit[7:1] Reserved
PME_En is not affected by Vcc POR, SOFT RESET
or HARD RESET
Bit[0] PME_Status
= 0 (default)
= 1 Set when FDC37B77x would normally assert the
Bit[7:1] Reserved
PME_Status is not affected by Vcc POR, SOFT
RESET or HARD RESET.
Writing a “1” to PME_Status will clear it and cause
the FDC37B77x to stop asserting nPME, in enabled.
PCI nPME signal, independent of the state of the
PME_En bit.
nPME signal assertion is disabled (default)
Enables FDC37B77x to assert nPME signal
154
DEFINITION
STATE
C
C
C