FDC37B77X SMSC Corporation, FDC37B77X Datasheet - Page 119

• Manufacturer Part Number: FDC37B77X
• Description: ENHANCED SUPER I/O CONTROLLER WITH WAKE UP FEATURES
• Manufacturer: SMSC Corporation

The FDC37B77x contains a Watch Dog Timer
(WDT). The Watch Dog Time-out status bit may
be
WDT_CFG Configuration Register.
The FDC37B77x's WDT has a programmable
time-out ranging from 1 to 255 minutes with one
minute resolution, or 1 to 255 seconds with 1
second resolution.
timeout value are selected via bit[7] of the
WDT_TIMEOUT register (LD8:CRF1.7). The
WDT
WDT_VAL Configuration register.
WDT_VAL register to 0x00 disables the WDT
function (this is its power on default). Setting
the WDT_VAL to any other non-zero value will
cause the WDT to reload and begin counting
down from the value loaded. When the WDT
count value reaches zero the counter stops and
sets the Watchdog time-out status bit in the
WDT_CTRL Configuration Register.
Regardless of the current state of the WDT, the
WDT time-out status bit can be directly set or
cleared by the Host CPU.
mapped
time-out
to
value
an
The units of the WDT
interrupt
is
set
through
through
Setting the
WATCH DOG TIMER
Note:
the
the
119
There are three system events which can reset
the WDT, these are a Keyboard Interrupt, a
Mouse Interrupt, or I/O reads/writes to address
0x201 (the internal or an external Joystick Port).
events may be individually enabled or disabled
through bits in the WDT_CFG configuration
register.
through the WDT_CFG register, the occurrence
of that event will cause the WDT to reload the
value stored in WDT_VAL and reset the WDT
time-out status bit if set.
events are disabled the WDT will inevitably time
out.
The Watch Dog Timer may be configured to
generate an interrupt on the rising edge of the
Time-out status bit.
mapped to an interrupt channel through the
WDT_CFG Configuration Register.
mapped to an interrupt the interrupt request pin
reflects the value of the WDT time-out status bit.
The host may force a Watch Dog time-out to
occur by writing a "1" to bit 2 of the WDT_CTRL
(Force WD Time-out) Configuration Register.
Writing a "1" to this bit forces the WDT count
value to zero and sets bit 0 of the WDT_CTRL
(Watch Dog Status). Bit 2 of the WDT_CTRL is
self-clearing.
The effect on the WDT for each of these system
When a system event is enabled
The WDT interrupt is
If all three system
When