FDC37B77X SMSC Corporation, FDC37B77X Datasheet - Page 155

• Manufacturer Part Number: FDC37B77X
• Description: ENHANCED SUPER I/O CONTROLLER WITH WAKE UP FEATURES
• Manufacturer: SMSC Corporation

PME Wake Status
Default = 0x00 on
V
PME Wake Enable
Default = 0x00 on
V
TR
TR
POR
POR
NAME
Table 64 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08]
(R/w Clear)
INDEX
(R/W)
0xC7
0xC8
REG
Writing a “0” to PME_Status has no effect.
This register indicates the state of the individual PME
wake sources, independent of the individual source
enables or the PME_En bit.
If the wake source has asserted a wake event, the
associated PME Wake Status bit will be a “1”.
Bit[0] CIR
Bit[1] RI2
Bit[2] RI1
Bit[3] KBD
Bit[4] MOUSE
Bit[7:5] Reserved
The PME Wake Status register is not affected by Vcc
POR, SOFT RESET or HARD RESET.
Writing a “1” to Bit[4:0] will clear it. Writing a “0” to
any bit in PME Wake Status Register has no effect.
This register is used to enable individual FDC37B77x
PME wake sources onto the nPME wake bus.
When the PME Wake Enable register bit for a wake
source is active (“1”), if the source asserts a wake
event and the PME_En bit is “1”, the source will
assert the PCI nPME signal.
When the PME Wake Enable register bit for a wake
source is inactive (“0”), the PME Wake Status
register will indicate the state of the wake source but
will not assert the PCI nPME signal.
Bit[0] CIR
Bit[1] RI2
Bit[2] RI1
Bit[3] KBD
Bit[4] MOUSE
Bit[7:5] Reserved
The PME Wake Enable register is not affected by Vcc
POR, SOFT RESET or HARD RESET.
Writing a “1” to Bit[4:0] will clear it. Writing a “0” to
any bit in PME Wake Enable register has no effect.
155
DEFINITION
STATE