FDC37B77X SMSC Corporation, FDC37B77X Datasheet - Page 124

• Manufacturer Part Number: FDC37B77X
• Description: ENHANCED SUPER I/O CONTROLLER WITH WAKE UP FEATURES
• Manufacturer: SMSC Corporation

Status Register
This register is cleared on a reset. This register
is read-only for the Host and read/write by the
FDC37B77x CPU.
UD
C/D
IBF
Writable by FDC37B77x CPU. These
bits are user-definable.
(Command Data)-This bit specifies
whether the input data register contains
data or a command (0 = data, 1 =
command).
data/command write operation, this bit
is set to "1" if SA2 = 1 or reset to "0" if
SA2 = 0.
(Input Buffer Full)- This flag is set to 1
whenever the host system writes data
into the input data register. Setting this
flag activates the FDC37B77x CPU's
nIBF (MIRQ) interrupt if enabled. When
the FDC37B77x CPU reads the input
data
automatically reset and the interrupt is
register
KCLK
KDAT
MCLK
MDAT
Host I/F Data Reg
Host I/F Status Reg
DESCRIPTION
(DBB),
During
this
a
N/A: Not Applicable
bit
Table 51 - Resets
host
is
124
HARDWARE RESET (RESET)
OBF
EXTERNAL CLOCK SIGNAL
The FDC37B77x Keyboard Controller clock
source is a 12 MHz clock generated from a
14.318 MHz clock. The reset pulse must last for
at least 24 16 MHz clock periods. The pulse-
width requirement applies to both internally (Vcc
POR) and externally generated reset signals. In
powerdown mode, the external clock signal is
not loaded by the chip.
DEFAULT RESET CONDITIONS
The FDC37B77x has one source of reset: an
external reset via the RESET_DRV pin. Refer to
Table 51 for the effect of each type of reset on
the internal registers.
cleared.
associated with this internal signal.
(Output Buffer Full) - This flag is set to
whenever the FDC37B77x CPU write to
the output data register (DBB). When
the host system reads the output data
register, this bit is automatically reset.
Input
Input
Input
Input
00H
N/A
There is no output pin