SPC5561MZQ132 Freescale Semiconductor / Motorola, SPC5561MZQ132 Datasheet - Page 11

• Manufacturer Part Number: SPC5561MZQ132
• Description: Power Architecture TM 32-bit MCU for Automotive
• Manufacturer: Freescale Semiconductor / Motorola

When powering down, V
capacitors internal and external to the device are already charged. When not powering up or down, no delta
between V
There are no power up/down sequencing requirements to prevent issues such as latch-up, excessive current
spikes, and so on. Therefore, the state of the I/O pins during power up and power down varies depending
on which supplies are powered.
Table 7
Table 8
pad_sh (slow type).
The values in
during power up.
Before exiting the internal POR state, the voltage on the pins goes to high-impedance until POR negates.
When the internal POR negates, the functional state of the signal during reset applies and the weak-pull
devices (up or down) are enabled as defined in the device Reference Manual. If V
propagate the logic signals, the weak-pull devices can pull the signals to V
To avoid this condition, minimize the ramp time of the V
required to enable the external circuitry connected to the device outputs.
3.7.1
When powering up the device, V
more than the V
bypass clock mode because the internal versions of PLLCFG[0:1] and RSTCFG are not powered and
Freescale Semiconductor
gives the pin state for the sequence cases for all pins with pad type pad_fc (fast type).
gives the pin state for the sequence cases for all pins with pad type pad_mh (medium type) and
RC33
Input Value of Pins During POR Dependent on V
Table 7
V
V
V
V
Table 8. Pin Status for Medium and Slow Pads During the Power Sequence
and V
Low
DD33
V
V
V
V
V
V
DDEH
DDEH
DDEH
DDEH
Low
DDE
DDE
DDE
DDE
DDE
DDE
lag specification listed in
DDSYN
and
Table 7. Pin Status for Fast Pads During the Power Sequence
V
Low
V
V
V
V
V
V
—
Low
Low
RC33
DD
DD
DD
DD33
DD33
DD33
DD33
—
Table 8
is required for the V
and V
Asserted
Asserted
Asserted
Negated
MPC5561 Microcontroller Data Sheet, Rev. 2.0
DD33
POR
V
Low
V
Low
V
V
—
do not include the effect of the weak-pull devices on the output pins
DD
DD
DD
DD
DDSYN
must not lag the latest V
Asserted
Asserted
Asserted
Asserted
Asserted
Negated
POR
Pin Status for Medium and Slow Pad Output Driver
have no delta requirement to each other, because the bypass
Table
RC
pad_mh (medium) pad_sh (slow)
to operate within specification.
Pin Status for Fast Pad Output Driver
6, spec 8. This avoids accidentally selecting the
High impedance (Hi-Z)
DD
High impedance (Hi-Z)
supply to a time period less than the time
Functional
DDSYN
Hi-Z
Low
pad_fc (fast)
Functional
High
High
Low
Hi-Z
or RESET power pin (V
DDE
DD33
and V
DD
Electrical Characteristics
is too low to correctly
DDEH
.
DDEH6
) by
11