SPC5561MZQ132 Freescale Semiconductor / Motorola, SPC5561MZQ132 Datasheet - Page 38

• Manufacturer Part Number: SPC5561MZQ132
• Description: Power Architecture TM 32-bit MCU for Automotive
• Manufacturer: Freescale Semiconductor / Motorola

Electrical Characteristics
3.13.7
38
1
2
3
4
5
6
7
Spec
10
11
12
All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type M or MH. DSPI signals using pad types
of S or SH have an additional delay based on the slew rate. DSPI timing is specified at: V
and CL = 50 pF with SRC = 0b11.
Speed is the nominal maximum frequency. Max. speed is the maximum speed allowed including frequency modulation (FM).
82 MHz parts allow for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM; and
135 MHz parts allow for 132 MHz system clock + 2% FM.
The minimum SCK cycle time restricts the baud rate selection for the given system clock rate.
These numbers are calculated based on two MPC55xx devices communicating over a DSPI link.
The actual minimum SCK cycle time is limited by pad performance.
The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK].
The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC].
This number is calculated using the SMPL_PT field in DSPI_MCR set to 0b10.
1
2
3
4
5
6
7
8
9
SCK cycle time
PCS to SCK delay
After SCK delay
SCK duty cycle
Slave access time
(SS active to SOUT driven)
Slave SOUT disable time
(SS inactive to SOUT Hi-Z, or invalid)
PCSx to PCSS time
PCSS to PCSx time
Data setup time for inputs
Data hold time for inputs
Data valid (after SCK edge)
Data hold time for outputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
DSPI Timing
Characteristic
3, 4
6
5
MPC5561 Microcontroller Data Sheet, Rev. 2.0
7
7
Symbol
Table 25. DSPI Timing
t
t
t
t
t
t
t
PCSC
PASC
t
t
CSC
SDC
SUO
t
SCK
ASC
DIS
SUI
t
HO
t
HI
A
(t
24.4 ns
SCK
– 2 ns
Min.
5.5
23
22
—
—
20
–4
20
–4
21
–4
—
—
—
—
–5
–5
4
5
2
7
8
÷ 2)
80 MHz
(t
2.9 ms
SCK
+ 2 ns
Max.
—
—
25
25
—
—
—
—
—
—
—
—
—
—
25
18
—
—
—
—
5
5
÷ 2)
1
’
2
(t
17.5 ns
SCK
– 2 ns
Min.
5.5
15
14
—
—
20
20
–4
14
–4
—
—
—
—
–5
–5
4
5
2
3
7
4
112 MHz
÷ 2)
(t
2.1 ms
SCK
+ 2 ns
Max.
25
25
25
14
DDEH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5
5
÷ 2)
= 3.0–5.5 V;T
(t
14.8 ns
SCK
– 2 ns
Freescale Semiconductor
Min.
5.5
13
12
20
20
–4
12
–4
–5
–5
—
—
—
—
—
—
4
5
2
6
7
3
132 MHz
÷ 2)
(t
1.8 ms
SCK
+ 2 ns
A
Max.
—
—
25
25
—
—
—
—
—
—
—
—
—
—
25
13
—
—
—
—
= T
5
5
÷ 2)
L
to T
Unit
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
H
;