SPC5561MZQ132 Freescale Semiconductor / Motorola, SPC5561MZQ132 Datasheet - Page 47

• Manufacturer Part Number: SPC5561MZQ132
• Description: Power Architecture TM 32-bit MCU for Automotive
• Manufacturer: Freescale Semiconductor / Motorola

5
The history of revisions made to this data sheet are shown in this section. The changes are divided into
each revision of this document. The substantive changes incorporated in MPC5561 Data Sheet Rev. 0.0 to
produce Rev. 1.0 of this document are grouped as follows:
Within each group, the changes are listed in sequential order.
5.1
The following table lists the global changes made throughout the document, as well as substantive changes
to text that is not in a table of figure.
Freescale Semiconductor
Global Changes
Section 1,
Sections 3.7.1, 3.7.2 and 3.7.3:
Section 3.7.1, “Input Value of Pins During POR Dependent on
Location
•
•
Global and text changes
Table and figure changes
“Overview”:
Information Changed Between Revisions 0.0 and 1.0
From: ‘To avoid accidentally selecting the bypass clock because PLLCFG[0:1] and RSTCFG are not treated as ones
(1s) when POR negates, V
by more than the V
pin (V
cannot lag both by more than the V
V
To:
‘When powering the device, V
V
internal versions of PLLCFG[0:1] and RSTCFG are not powered and therefore cannot read the default state when
POR negates. V
V
requirements when powering down.’
Revision History for the MPC5561 Data Sheet
• Replaced kilobytes with KB.
• Replaced megabytes with MB.
• First paragraph: text changed from “. . . based on the PowerPC Book E architecture” to “. . . built on the Power
• Second paragraph: Changed terminology from PowerPC Book E architecture to Power Architecture terminology.
• Added new third paragraph about VLE feature.
• Added new eighth paragraph about the parallel digital interface (PDI).
• Paragraph nine: changed “the MPC5561 has an on-chip 20-channel enhanced queued analog-to-digital
• Added the sentence preceding
•
•
•
DD33
DD33
DD33
Architecture embedded technology.”
converter (eQADC)” to “. . . has an on-chip 40-channel dual enhanced queued . . .”
Section 3.7.1, “Input Value of Pins During POR Dependent on
Section 3.7.2, “Power-Up Sequence (VRC33
Section 3.7.3, “Power-Down Sequence (VRC33
throughout the document
DDEH6
has no lead or lag requirements when powering down.’
lag specification listed in
lag specification. This V
Table 27. Global and Text Changes Between Rev. 0.0 and Rev. 1.0
) by more than the V
DD33
DD33
Reordered sections resulting in the following order and section renumbering:
can lag V
lag specification in
DD33
MPC5561 Microcontroller Data Sheet, Rev. 2.0
DD33
DD33
DDSYN
must not lag V
Table
DD33
Table
DD33
must not lag V
lag specification only applies during power up. V
lag specification. V
6. This avoids accidentally selecting the bypass clock mode because the
or the RESET power pin (V
lag specification. This V
1: ‘Unless noted in this data sheet, all specifications apply from T
Table
Description of Changes
DDSYN
Grounded),” then
6. V
DDSYN
VDD33,” changed:
Grounded).
and the RESET pin power (V
DD33
and the RESET power pin (V
DD33
individually can lag either V
can lag one of the V
DD33
VDD33,” then
DDEH6
Revision History for the MPC5561 Data Sheet
lag specification only applies during power up.
), but cannot lag both by more than the
DDEH6
DDSYN
DD33
DDEH6
DDSYN
) when powering the device
or V
has no lead or lag
) by more than the
or the RESET power
DDEH6
supplies, but
L
to T
H
47
.’