SPC5561MZQ132 Freescale Semiconductor / Motorola, SPC5561MZQ132 Datasheet - Page 51

• Manufacturer Part Number: SPC5561MZQ132
• Description: Power Architecture TM 32-bit MCU for Automotive
• Manufacturer: Freescale Semiconductor / Motorola

Freescale Semiconductor
Table 9
Figure 3
Table 12
Location
DC Electrical Specifications: (continued)
Added figure to show interpolated IDD
FMPLL Electrical Characteristics:
• Spec 27c, Operating current 1.5 V supplies @ 82 MHz: Added maximum values for 8-way cache:
• Spec 28: Changed 132 MHz to 135 MHz.
• Spec 29: Deleted frequency information.
• Corrected footnote 3 to read: If standby operation is not required, connect the V
• Combined old footnotes 11 and 12 for new footnote 6 and added to specs 27a, b, and c on the 8-way cache line
• Added footnote 10 to specs 27a, b, and c on the 4-way cache line that reads: Four-way cache enabled
• Added footnote 11 to specs 27a, b, and c on the max numeric values: “Preliminary. Specification pending final
• Added footnote 12 to specs 27a, b, and c on the max TBD values: “Specification pending final characterization.”
• Added (T
• Spec 1, footnote 1 in column 2: ‘PLL reference frequency range.’: Changed to read ‘Nominal crystal and external
• Spec 1, added two more lines to the PLL reference frequency range’ to read as follows:
• Spec 1, footnote 2 in column 2: ‘PLL reference frequency range.’: Changed to: ‘The 8–20 MHz crystal or external
• Spec 1, footnote 2 in column 2: ‘PLL reference frequency range,’ Changed to: The 20–40 MHz crystal and
• Specs 12 and 13: Grouped (2 x Cl).
• Spec 21, column 2: Changed f
• Spec 21, column 4, Max.: Deleted old footnote 18 that reads:
• Spec 21: Changed column 5 from ‘82 or 66 MHz’ to: ‘150’.
• Spec 22: Changed column 4, Max. Value from f
that reads: Eight-way cache enabled (L1CSR0[CORG] = 0b0).
(L1CSR0[CORG] = 0b1) or (L1CSR0[CORG] = 0b0 with L1CSR0[WAM] = 0b1, L1CSR0[WID] = 0b1111,
L1CSR0[WDD] = 0b1111, L1CSR0[AWID] = 0b1, and L1CSR0[AWDD] = 0b1).
characterization.”
reference values are worst-case not more than 1%. The device operates correctly if the frequency remains within
± 5% of the specification limit. This tolerance range allows for a slight frequency drift of the crystals over time.
The designer must thoroughly understand the drift margin of the source clock.‘
reference values have PLLCFG[2] pulled low’ and applies to spec 1, column 2, crystal reference and external
reference.
external reference values have PLLCFG[2] pulled high, and the minimum frequency must be greater than 20
MHz. Use the 8–20 MHz setting (PLLCFG[2] pulled low) if a 20 MHz crystal or external reference is required. To
exit RESET when using 40 MHz, set PLLCFG[2] to 1.
added the same equation but substituted f
f
f
The ICO frequency can be higher than the maximum allowable system frequency. For this case, set the CMPLL
synthesizer control register reduced frequency divider (FMPLL_SYNCR[RFD]) to divide-by-two (RFD = 0b001).
Therefore, for a 40 MHz maximum device (system frequency), program the FMPLL to generate 80 MHz at the
ICO output and then divide-by-two the RFD to provide the 40 MHz system clock.’
dual controller (1:1) mode is (f
crystal reference (20)
crystal reference (40)
external reference (20)
external reference (40)
ico
ico
1.65 typical = 490,
1.35 typical = 360,
1.65 high = 520,
1.35 high = 390.
All 8-way cache max values have footnote 11.
Added 4-way cache values
1.65 high = TBD and 1.35 high = TBD, both with footnote 12.
= [ f
= [ f
Table 28. Table and Figure Changes Between Rev. 0.0 and 1.0 (continued)
ref_crystal
ref_ext
A
= T
× (MFD + 4) ] ÷ (PREDIV + 1)
L
– T
× (MFD + 4) ] ÷ (PREDIV + 1)
H
) to the second line of the table title.
MPC5561 Microcontroller Data Sheet, Rev. 2.0
MAX
ref_crystal
STBY
fref_crystal
fref_crystal
÷ 2) and the predivider set to 1 (FMPLL_SYNCR[PREDIV] = 0b001).’
fref_ext
fref_ext
values listed in
to f
Description of Changes
ref_ext
ref
in ICO frequency equation, and
MAX
for f
to 20, and added footnote 20 to read, ‘Maximum value for
> 20
ref
> 20
Table
8
for the external reference clock, giving:
8
9.
≤ 20
≤ 20
Revision History for the MPC5561 Data Sheet
40
40
STBY
to ground.
51