MT16VDDT3264 Micron, MT16VDDT3264 Datasheet - Page 14

• Manufacturer Part Number: MT16VDDT3264
• Description: 184-Pin DDR SDRAM DIMMs (x64)
• Manufacturer: Micron

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS*
(Notes: 1–5, 12–15, 29; notes appear following parameter tables)
(0°C ≤ T
*Module AC timing parameters comply with PC1600, PC2100, and PC2700 design specifications, based on DDR SDRAM component
32, 64 Meg x 64 DDR SDRAM DIMMs
DD16C32_64X64AG_C.p65 – Rev. C; Pub. 3/02
PARAMETER
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
ACTIVE to PRECHARGE command
ACTIVE to READ with auto precharge command,
(512MB Modules)
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time
DQS write postamble
Write recovery time
Internal WRITE to READ command delay
AC CHARACTERISTICS
ACTIVE to READ with auto precharge command,
(256MB Modules)
performance parameters.
A
≤ +70°C; V
DD
Q = +2.5V ±0.2V, V
CL = 2.5
DD
CL = 2
= +2.5V ±0.2V)
t
t
t
CK (2.5)
t
t
DQSCK
t
t
WPRES
t
t
t
t
DQSQ
t
t
CK (2)
DQSH
t
WPRE
WPST
t
SYM
DIPW
DQSL
DQSS
t
t
t
t
t
t
t
t
MRD
t
RPRE
RPST
t
WTR
t
DSH
t
t
QHS
t
t
t
t
t
t
t
RAS
RAP
RAP
RCD
RRD
t
DSS
t
t
RFC
t
WR
DH
AC
CH
DS
HP
HZ
IH
IH
RC
CL
LZ
IS
IS
RP
F
F
S
S
14
t
CH,
-0.70
-0.60
-0.70
MIN
0.45
0.45
0.45
0.45
1.75
0.35
0.35
0.75
0.75
0.75
0.80
0.80
0.25
18
18
7.5
0.2
0.2
t
0.9
0.4
0.4
12
42
60
72
18
18
12
15
HP -
6
0
1
t
CL
-335
t
QHS
70,000
+0.70
+0.60
+0.70
MAX
0.55
0.55
0.45
1.25
0.60
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1.1
0.6
0.6
12
12
184-PIN DDR SDRAM DIMMs
t
7.5/10
CH,
t
-0.75
-0.75
-0.75
MIN
RAS(MIN) - (burst length *
0.45
0.45
1.75
0.35
0.35
0.75
0.90
0.90
0.25
7.5
0.5
0.5
0.2
0.2
0.9
0.4
0.4
15
40
20
65
75
20
20
15
15
-26A/-265
1
1
t
0
1
HP -
t
CL
t
QHS
120,000
+0.75
+0.75
+0.75
MAX
256MB, 512MB (x64)
0.55
0.55
1.25
0.75
1.1
0.6
0.6
0.5
13
13
t
CH,
MIN
0.45
0.45
0.35
0.35
0.75
0.25
-0.8
-0.8
-0.8
0.2
0.2
1.1
1.1
1.1
1.1
0.9
0.4
0.4
0.6
0.6
10
16
40
20
70
80
20
20
15
15
0
8
2
1
t
t
HP -
CL
-202
t
120,000
QHS
t
MAX
CK/2)
+0.8
0.55
0.55
+0.8
1.25
+0.8
0.6
1.1
0.6
0.6
13
13
1
©2002, Micron Technology, Inc.
UNITS
t
t
t
t
t
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
CK
CK
CK
CK
CK
CK
ns
CK
CK
CK
CK
CK
ns
ns
NOTES
40, 47
40, 47
23, 27
23, 27
22, 23
16, 37
22, 23
18, 19
16, 38
26
26
27
30
12
12
12
12
31
41
41
45
37
17