MT16VDDT3264 Micron, MT16VDDT3264 Datasheet - Page 19

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MT16VDDT3264

Manufacturer Part Number
MT16VDDT3264
Description
184-Pin DDR SDRAM DIMMs (x64)
Manufacturer
Micron
Datasheet
NOTES (continued)
40. The current Micron part operates below the
41.
42. For the -335, -265 and -26A modules, I
43. Random addressing changing 50% of data
44. Random addressing changing 100% of data
45. CKE must be active (high) during the entire time
46. IDD2N specifies the DQ, DQS, and DM to be
47. Whenever the operating frequency is altered, not
48. Leakage number reflects the worst case leakage
32, 64 Meg x 64 DDR SDRAM DIMMs
DD16C32_64X64AG_C.p65 – Rev. C; Pub. 3/02
slowest JEDEC operating frequency of 83 MHz.
As such, future die may not reflect this option.
t
specified to be 35mA at 100 MHz.
changing at every transfer.
changing at every transfer.
a refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge,
until
driven to a valid high or low logic level. IDD2Q is
similar to IDD2F except IDD2Q specifies the
address and control inputs to remain stable.
Although IDD2F, IDD2N, and IDD2Q are similar,
IDD2F is “worst case.”
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles.
possible through the module pin, not what each
RAP ≥
memory device contributes.
t
REF later.
t
RCD.
DD
3N is
19
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM DIMMs
256MB, 512MB (x64)
©2002, Micron Technology, Inc.

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