MT16VDDT3264 Micron, MT16VDDT3264 Datasheet - Page 9

• Manufacturer Part Number: MT16VDDT3264
• Description: 184-Pin DDR SDRAM DIMMs (x64)
• Manufacturer: Micron

EXTENDED MODE REGISTER
yond those controlled by the mode register; these addi-
tional functions are DLL enable/disable, output drive
strength, and QFC#. These functions are controlled via
the bits shown in the Extended Mode Register Defini-
tion Diagram. The extended mode register is pro-
grammed via the LOAD MODE REGISTER command to
the mode register (with BA0 = 1 and BA1 = 0) and will
retain the stored information until it is programmed
again or the device loses power. The enabling of the DLL
should always be followed by a LOAD MODE REGISTER
command to the mode register (BA0/BA1 both LOW) to
reset the DLL.
device banks are idle and no bursts are in progress, and
the controller must wait the specified time before initiat-
ing any subsequent operation. Violating either of these
requirements could result in unspecified operation.
Output Drive Strength
fied to be SSTL2, Class II. For detailed information on
output drive strength option, refer to 128Mb and
256Mb DDR SDRAM data sheets.
DLL Enable/Disable
DLL enable is required during power-up initialization
and upon returning to normal operation after having
disabled the DLL for the purpose of debug or evalua-
tion. (When the device exits self refresh mode, the DLL
is enabled automatically.) Any time the DLL is enabled,
200 clock cycles must occur before a READ command
can be issued.
32, 64 Meg x 64 DDR SDRAM DIMMs
DD16C32_64X64AG_C.p65 – Rev. C; Pub. 3/02
The extended mode register controls functions be-
The extended mode register must be loaded when all
The normal full drive strength for all outputs is speci-
The DLL must be enabled for normal operation.
9
512MB Module
256MB Module
Extended Mode Register Definition
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM DIMMs
NOTE: 1. E13 and E12 (256MB module), or E14 and E13 (512MB Module)
E12
0
–
E11
0 1
14
BA1 BA0
0
–
2. The QFC# option is not supported.
1 1
E10
13
0 1
0
13
–
BA1 BA0
(BA1 and BA0) must be “0, 1” to select the Extended
Mode Register (vs. the base Mode Register).
12
E9
1 1
A12
0
–
12
11
E8
256MB, 512MB (x64)
A11
0
–
11
A11
10
E7
Diagram
0
–
A10
10
A10
Operating Mode
E6 E5
0
–
9
A9
9
A9
0
–
8
Operating Mode
A8
8
A8
E4
0
–
7
A7 A6 A5 A4 A3
7
A7 A6 A5 A4 A3
E3
0
–
6
6
5
5
E2,
Valid
4
E1,
4
–
E0
3
3
QFC#
QFC
2
E2
A2 A1 A0
2
0
–
©2002, Micron Technology, Inc.
A2 A1 A0
3
DS
Operating Mode
Reserved
Reserved
DS
1
1
E1 2
DLL
0
DLL
0
0
E0
0
1
QFC# Function
Drive Strength
Extended Mode
Register (Ex)
Disabled
Reserved
Extended Mode
Register (Ex)
Address Bus
Address Bus
Normal
Disable
Enable
DLL