MT16VDDT3264 Micron, MT16VDDT3264 Datasheet - Page 7

• Manufacturer Part Number: MT16VDDT3264
• Description: 184-Pin DDR SDRAM DIMMs (x64)
• Manufacturer: Micron

that can be accessed for a given READ or WRITE com-
mand. Burst lengths of 2, 4, or 8 locations are available
for both the sequential and the interleaved burst types.
operation or incompatibility with future versions may
result.
of columns equal to the burst length is effectively se-
lected. All accesses for that burst take place within this
block, meaning that the burst will wrap within the block
if a boundary is reached. The block is uniquely se-
lected by A1-Ai when the burst length is set to two, by
A2-Ai when the burst length is set to four and by A3-Ai
when the burst length is set to eight (where Ai is the
32, 64 Meg x 64 DDR SDRAM DIMMs
DD16C32_64X64AG_C.p65 – Rev. C; Pub. 3/02
512MB Module
256MB Module
Reserved states should not be used, as unknown
When a READ or WRITE command is issued, a block
* M14 and M13 (BA1 and BA0)
Mode Register Definition
* M13 and M12 (BA1and BA0)
must be “0, 0” to select the
must be “0, 0” to select the
base mode register (vs. the
base mode register (vs. the
extended mode register).
extended mode register).
0*
14
BA1
0*
0*
13
13
BA1
BA0
0*
12
12
BA0
A12 A11
Operating Mode
11
11
A11
Operating Mode
10
10
A10
A10
M12 M11
Diagram
0
0
-
9
9
A9
A9
0
0
-
8
8
A8
A8
M10
0
0
-
7
7
A7 A6 A5 A4 A3
A7 A6 A5 A4 A3
M9
M6
0
0
CAS Latency BT
CAS Latency BT
-
0
0
0
0
1
1
1
1
6
6
M8 M7
M5
0
1
-
0
0
1
1
0
0
1
1
5
5
0
0
-
M4
0
1
0
1
0
1
0
1
4
4
M3
M6-M0
0
1
Valid
Valid
3
3
-
Burst Length
Burst Length
M2
0
0
0
0
1
1
1
1
2
2
A2 A1 A0
A2 A1 A0
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
M1
0
0
1
1
0
0
1
1
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
1
1
2.5
2
M0
0
1
0
1
0
1
0
1
0
0
Interleaved
Burst Type
Sequential
Reserved
Reserved
Reserved
Reserved
Reserved
Mode Register (Mx)
Mode Register (Mx)
M3 = 0
Address Bus
Address Bus
2
4
8
Burst Length
Reserved
Reserved
Reserved
Reserved
Reserved
M3 = 1
2
4
8
7
most significant column address bit for a given con-
figuration). The remaining (least significant) address
bit(s) is (are) used to select the starting location within
the block. The programmed burst length applies to
both READ and WRITE bursts.
Burst Type
be either sequential or interleaved; this is referred to as
the burst type and is selected via bit M3.
by the burst length, the burst type and the starting
column address, as shown in Burst Definition Table.
NOTE: 1. For a burst length of two, A1-Ai select the two-
i = 11 for 256MB module, or 12 for 512MB module
Length
Burst
Accesses within a given burst may be programmed to
The ordering of accesses within a burst is determined
2
4
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM DIMMs
2. For a burst length of four, A2-Ai select the four-
3. For a burst length of eight, A3-Ai select the eight-
4. Whenever a boundary of the block is reached
Starting Column
data-element block; A0 selects the first access
within the block.
data-element block; A0-A1 select the first access
within the block.
data-element block; A0-A2 select the first access
within the block.
within a given sequence above, the following
access wraps within the block.
A2 A1 A0
0
0
0
0
1
1
1
1
Address
A1 A0
0
0
1
1
0
0
1
1
0
0
1
1
Burst Definition
A0
256MB, 512MB (x64)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Table
Type = Sequential
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Order of Accesses Within a Burst
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1
1-0
Type = Interleaved
©2002, Micron Technology, Inc.
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0