MT16VDDT3264 Micron, MT16VDDT3264 Datasheet - Page 18

• Manufacturer Part Number: MT16VDDT3264
• Description: 184-Pin DDR SDRAM DIMMs (x64)
• Manufacturer: Micron

NOTES (continued)
28. V
29. The clock is allowed up to ±150ps of jitter. Each
30.
31. READs and WRITEs with auto precharge are not
32. Any positive glitch must be less than
33. Normal Output Drive Curves:
32, 64 Meg x 64 DDR SDRAM DIMMs
DD16C32_64X64AG_C.p65 – Rev. C; Pub. 3/02
160
140
120
100
80
60
40
20
0
active while any bank is active.
timing parameter is allowed to vary by the same
amount.
t
minimum actually applied to the device CK and
CK/ inputs, collectively during bank active.
allowed to be issued until
satisfied prior to the internal precharge com-
mand being issued.
clock and not more than +400mV or 2.9 volts,
whichever is less. Any negative glitch must be
less than
either -300mV or 2.2 volts, whichever is more
positive.
a) The full variation in driver pull-down current
b)The variation in driver pull-down current
c) The full variation in driver pull-up current from
d)The variation in driver pull-up current within
HP min is the lesser of
0.0
DD
from minimum to maximum process, tempera-
ture and voltage will lie within the outer
bounding lines of the V-I curve of Figure A.
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure A.
minimum to maximum process, temperature
and voltage will lie within the outer bounding
lines of the V-I curve of Figure B.
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within
the inner bounding lines of the V-I curve of
Figure B.
must not vary more than 4% if CKE is not
1
/
0.5
3
of the clock cycle and not exceed
Pull-Down Characteristics
1.0
Figure A
V
t
OUT
CL minimum and
t
(V)
RAS
1.5
(MIN)
can be
1
/
3
2.0
of the
t
CH
2.5
18
34. The voltage levels used are derived from a
35. VIH overshoot: VIH(MAX) = V
36. V
37. This maximum value is derived from the
38. For slew rates greater than 1V/ns the (LZ)
39. During initialization, V
-100
-120
-140
-160
-180
-200
-20
-40
-60
-80
e) The full variation in the ratio of the maximum to
f) The full variation in the ratio of the nominal
minimum V
In practice, the voltage levels obtained from a
properly terminated bus will provide significantly
different voltage values.
pulse width ≤ 3ns and the pulse width can not be
greater than 1/3 of the cycle rate. VIL under-
shoot: VIL(MIN) = -1.5V for a pulse width ≤ 3ns
and the pulse width can not be greater than 1/3
of the cycle rate.
referenced test load. In practice, the values
obtained in a typical terminated design may
reflect up to 310ps less for
DVW.
t
t
transition will start about 310ps earlier.
equal to or less than V
may be 1.35V maximum during power up, even
if V
42 ohms of series resistance is used between the
V
0
RPST(MAX) condition.
DQSCK(MIN) +
0.0
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
TT
minimum pull-up and pull-down current
should be between .71 and 1.4, for device drain-
to-source voltages from 0.1V to 1.0 Volt, and at
the same voltage and temperature.
pull-up to pull-down current should be unity
±10%, for device drain-to-source voltages from
0.1V to 1.0 Volt.
184-PIN DDR SDRAM DIMMs
DD
supply and the input pin.
and V
/V
t
HZ(MAX) will prevail over
DDQ
DDQ
0.5
DD
are 0 volts, provided a minimum of
must track each other.
Pull-Up Characteristics
level and the referenced test load.
256MB, 512MB (x64)
t
RPRE(MAX) condition.
Figure B
1.0
V
DD
DD
DDQ
Q - V
t
LZ(MIN) will prevail over
+ 0.3V. Alternatively, V
, V
OUT
t
HZ(MAX) and the last
TT
(V)
1.5
, and V
DD
t
DQSCK(MAX) +
Q+1.5V for a
©2002, Micron Technology, Inc.
REF
2.0
must be
TT
2.5