MT16VDDT3264 Micron, MT16VDDT3264 Datasheet - Page 17

• Manufacturer Part Number: MT16VDDT3264
• Description: 184-Pin DDR SDRAM DIMMs (x64)
• Manufacturer: Micron

21. The refresh period 64ms. This equates to an
22. The valid data window is derived by achieving
23. Referenced to each output group: x8 = DQS with
32, 64 Meg x 64 DDR SDRAM DIMMs
DD16C32_64X64AG_C.p65 – Rev. C; Pub. 3/02
NOTES (continued)
average refresh rate of 15.625µs (256MB
modules), or 7.821µs (512MB modules). How-
ever, an AUTO REFRESH command must be
asserted at least once every 140.6µs (256MB
modules) or 70.3µs (512MB modules); burst
refreshing or posting by the DRAM controller
greater than eight refresh cycles is not allowed.
other specifications -
t
derates directly porportional with the clock duty
cycle and a practical data valid window can be
derived. The clock is allowed a maximum duty
cycle variation of 45/55. Functionality is uncer-
tain when operating beyond a 45/55 ratio. The
data valid window derating curves are provided
below for duty cycles ranging between 50/50 and
45/55.
DQ0-DQ7.
QH (
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
t
QH =
50/50
3.750
2.500
t
3.400
HP -
TBD -335 @
—— -265/-26A @
—— -202 @
TBD -335 @
—— -265/-26A @
—— -202 @
#
u
n
l
49.5/50.5
t
QHS). The data valid window
3.700
3.350
2.463
t
t
t
t
t
CK = 7.5ns
HP (
CK = 10ns
CK = 8ns
CK = 6ns
t
t
CK = 7.5ns
CK = 10ns
t
3.650
49/51
CK/2),
2.425
3.300
t
48.5/52.5
DQSQ, and
3.600
2.388
3.250
DERATING DATA VALID WINDOW
3.550
48/52
2.350
3.200
Clock Duty Cycle
(
t
QH -
17
47.5/53.5
3.500
t
DQSQ)
2.313
3.150
24. This limit is actually a nominal value and does
25. To maintain a valid level, the transitioning edge
26. JEDEC specifies CK and CK# input slew rate must
27. DQ and DM input slew rates must not deviate
not result in a fail value. CKE is HIGH during
REFRESH command period (
CKE is LOW (i.e., during standby).
of the input must:
a) Sustain a constant slew rate from the current
b) Reach at least the target AC level.
c) After the AC target level is reached, continue
be ≥ 1V/ns (2V/ns differentially).
from DQS by more than 10%. If the DQ/DM/DQS
slew rate is less than 0.5V/ns, timing must be
derated: 50ps must be added to
each 100mv/ns reduction in slew rate. If slew rate
exceeds 4V/ns, functionality is uncertain.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
AC level through to the target AC level, V
or V
or V
3.450
47/53
to maintain at least the target DC level, V
184-PIN DDR SDRAM DIMMs
2.275
3.100
IH
IH
(
(
AC
DC
46.5/54.5
).
).
3.400
2.238
3.050
256MB, 512MB (x64)
3.350
46/54
2.200
3.000
45.5/55.5
3.300
t
RFC [MIN]) else
2.163
2.950
t
DS and
©2002, Micron Technology, Inc.
3.250
45/55
2.900
2.125
IL
t
(
DH for
IL
AC
(
DC
)
)