MT90870 Zarlink Semiconductor, Inc., MT90870 Datasheet - Page 18

• Manufacturer Part Number: MT90870
• Description: Flexible 12k Digital Switch (F12kDX)
• Manufacturer: Zarlink Semiconductor, Inc.

MT90870
3.3
This feature is used to advance the output channel alignment of individual Local or Backplane output streams
with respect to the frame boundary. Each output stream has its own advancement value which can be
programmed by the output advancement registers. The output advancement selection is useful in
compensating for various parasitic loading on the serial data output pins.
3.3.1
The Local output advancement registers, LOAR0-15, are used to control the Local output advancement. The
advancement is determined with reference to the internal system clock rate (131.072MHz). For 2Mb/s, 4Mb/s,
8Mb/s or 16Mb/s streams the advancement may be 0, -2 cycles, -4 cycles or -6 cycles, which converts to
approximately 0ns, -15ns, -30ns or -45ns as shown in Figure 11.
3.3.2
The Backplane output advancement registers, BOAR0-31 are used to control the Backplane output
advancement. The advancement is determined with reference to the internal system clock rate (131.072MHz).
For 2Mb/s, 4Mb/s, 8Mb/s or 16Mb/s streams the advancement may be 0, -2 cycles, -4 cycles or -6 cycles,
which converts to approximately 0ns, -15ns, -30ns or -45ns as shown in Figure 11. For 32Mb/s streams, the
advancement may be 0, -1 cycle, -2 cycles or -3 cycles, which converts to approximately 0ns, -7ns, -15ns or
18
-22ns.
BSTi0-31/LSTi0-15
BSTi0-31/LSTi0-15
BSTi0-31/LSTi0-15
BSTi0-31/LSTi0-15
BSTi0-31/LSTi0-15
BSTi0-31/LSTi0-15
BSTi0-31/LSTi0-15
Figure 10 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 8Mb/s
Bit Delay = 7
Bit Delay = 7
Bit Delay = 1/2
Output Advancement Programming (Backplane and Local Output Streams)
Local Output Advancement Programming
Backplane Output Advancement Programming
Bit Delay = 1/4
Bit Delay = 3/4
Bit Delay = 1
Bit Delay = 0
(Default)
FP8o
C8o
1/2
3/4
3
Ch126
3
Ch126
3
Ch127
2
3
Ch127
2
Ch127
2
3
Ch127
2
Ch127
2
1
2
1
1
2
1
1
0
1
0
0
1
0
0
7
0
7
0
7
7
Bit Delay, 1/4
7
6
Bit Delay, 1/2
7
6
Bit Delay, 3/4
6
7
Bit Delay, 1
6
6
5
6
5
5
6
5
Ch127
5
Ch127
4
Ch0
5
4
4
5
Ch0
Ch0
4
Ch0
3
4
3
Ch0
4
3
4
3
3
2
3
2
2
3
2
2
1
2
1
1
2
1
1
0
1
0
0
1
0
0
7
0
7
Bit Delay, 7
Preliminary Information
7
0
Bit Delay, 7
7
7
6
7
6
6
7
6
1/2
6
Ch0
5
3/4
6
Ch0
5
Ch1
5
6
Ch1
Ch1
5
Ch1
5
4
Ch1
5
4
4
5
4
4
4