MT90870 Zarlink Semiconductor, Inc., MT90870 Datasheet - Page 48

• Manufacturer Part Number: MT90870
• Description: Flexible 12k Digital Switch (F12kDX)
• Manufacturer: Zarlink Semiconductor, Inc.

MT90870
13.5
Address 0023h to 0032h.
Sixteen Local input delay registers (LIDR0 to LIDR15) allow users to program the input bit delay for the Local
input data streams LSTi0-15. The possible adjustment is up to 7 3/4 of the data rate, advancing forward with a
resolution of 1/4 of the data rate. The data rate can be either 2Mb/s, 4Mb/s, 8Mb/s or 16Mb/s.
The LIDR0 to LIDR15 registers are configured as follows:
13.5.1
These five bits define the delay from the bit boundary that the receiver uses to sample each input. Input bit
delay adjustment can range up to 7
This can be described as: LIDn(4:0) = (no. of bits delay) / 4
For example, if LIDn(4:0) is set to 10011 (19), the input bit delay = 19 *
Table 22, Local Input Bit Delay Programming Table, illustrates the bit delay selection.
48
LIDRn Bit
(where n = 0
to 15)
15-5
4-0
0 (Default)
Data Rate
1 1/4
1 1/2
1 3/4
2 1/4
2 1/2
2 3/4
3 1/4
3 1/2
3 3/4
1/4
1/2
3/4
1
2
3
Local Input Bit Delay Registers (LIDR0 to LIDR15)
Local Input Delay Bits 4-0 (LID4 - LID0)
Reserved
LIDn(4:0)
Name
Table 21 - Local Channel Delay Register (LIDRn) Bits
Table 22 - Local Input Bit Delay Programming Table
LID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
/
4
Reset
bit periods forward, with resolution of
0
0
LID3
Reserved
Local Input Bit Delay Register
The binary value of these bits refers to the input bit delay value
for the Local input stream
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Corresponding Delay Bits
LID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
Description
/
4
= 4
1
/
4
3
/
Preliminary Information
4.
bit period.
LID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
LID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1