MT90870 Zarlink Semiconductor, Inc., MT90870 Datasheet - Page 58
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MT90870
Manufacturer Part Number
MT90870
Description
Flexible 12k Digital Switch (F12kDX)
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet
1.MT90870.pdf
(77 pages)
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Part Number:
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MT90870
13.11.3
Address 00CAh
Backplane Receive BER Length Register (BRXBLR) defines how many channels in each frame the BER
sequence will be transmitted. The BRXBLR register is configured as follows:
13.11.4
Address 00CBh
Backplane BER Start Receive Register defines the Input Stream and the Start Channel in which the BER
sequence shall be received. The BBSRR register is configured as follows:
13.11.5
Address 00CCh
Backplane BER Count Register contains the number of counted errors. This register is read only. The BBCR
register is configured as follows:
58
15-14
13-9
15-9
15-0
8-0
Bit
8-0
Bit
Bit
BBRCA(8:0)
BBRSA(4:0)
BRXBL(8:0)
Backplane Receive BER Length Register (BRXBLR)
Backplane BER Start Receive Register (BBSRR)
Backplane BER Count Register (BBCR)
BBC(15:0)
Reserved
Reserved
Name
Name
Name
Table 39 - Backplane BER Start Receive Register (BBSRR) Bits
Table 38 - Backplane Receive BER Length (BRXBLR) Bits
Reset
Table 40 - Backplane BER Count Register (BBCR) Bits
Reset
Reset
0
0
0
0
0
0
Reserved.
Backplane Receive BER Length Bits
The binary value of these bits define the number of channels in addition to the
Start Channel allocated for the BER receiver. (i.e. Total Channels = Start
Channel + BRXBL value)
Reserved.
Backplane BER Receive Stream Address Bits
The binary value of these bits defines the Backplane input stream that
receives the BER data.
Backplane BER Receive Channel Address Bits
The binary value of these bits define the Backplane input start channel in
which the BER data will be received.
Backplane Bit Error Rate Count
The binary value of these bits define the Backplane Bit Error count.
Description
Description
Description
Preliminary Information