MT90870 Zarlink Semiconductor, Inc., MT90870 Datasheet - Page 24

• Manufacturer Part Number: MT90870
• Description: Flexible 12k Digital Switch (F12kDX)
• Manufacturer: Zarlink Semiconductor, Inc.

MT90870
4.2
The input pin, BORS, selects whether the Backplane output streams, BSTo0-31 are set to high impedance at
the output of the MT90870 itself, or are always driven (active HIGH or active LOW) and a high impedance
state, if required on a per-channel basis, is invoked through an external interface circuit controlled by the
BCSTo0-3 signals. Setting BORS to a LOW state will configure the output streams, BSTo0-31, to transmit bi-
state channel data with per-channel high-impedance determined by external circuits under the control of the
BCSTo0-3 outputs.
MT90870 to invoke a high-impedance output on a per-channel basis.
The BORS pin is an asynchronous input and is expected to be hard-wired for a particular system application,
although it may be driven under logic control if preferred.
4.2.1
The data (channel control bit) transmitted by BCSTo0-3 replicates the Backplane Output Enable Bit (BE) of
the Backplane Connection Memory, with a LOW state indicating the channel be set to High Impedance. Section
12.4, Backplane Connection Memory Bit Definition, refers.
The BCSTo0-3 outputs transmit serial data (channel control bits) at 16.384Mb/s, with each bit representing the
per-channel high impedence state for specific streams. Eight output streams are allocated to each control line
as follows:
(See also Pin Description)
•
•
•
•
The Channel Control Bit location, within a frame period, for each channel of the Backplane output streams is
presented in Table 3,
As an aid to the description, the channel control bit for a single channel on specific streams is presented, with
reference to Table 3:
(1) The Channel Control Bit corresponding to Stream 0, Channel 0, BSTo0_Ch0, is transmitted on BCSTo0
and is advanced, relative to the Frame Boundary, by 10 periods of C16o.
(2) The Channel Control Bit corresponding to Stream 28, Channel 0, BSTo28_Ch0, is transmitted on BCSTo0
in advance of the Frame Boundary by three periods of output clock, C16o. Similarly, the Channel Control Bits
for BSTo29_Ch0, BSTo30_Ch0 and BSTo31_Ch0 are advanced relative to the Frame Boundary by three
periods of C16o, on BCSTo1, BCSTo2 and BCSTo3, respectively.
The BCSTo0-3 outputs data at a constant data-rate of 16.384Mb/s, independent of the data-rate selected for
the individual output streams, BSTo0-31. Streams at data-rates lower than 16.384Mb/s will have the value of
the respective channel control bit repeated for the duration of the channel. The bit will be repeated twice for
8.192Mb/s streams, four times for 4.096Mb/s streams and eight times for 2.048Mb/s streams. The channel
control bit is not repeated for 16.384Mb/s streams.
Examples are presented, with reference to Table 3:
24
BCSTo0 outputs the channel control bits for streams BSTo0, 4, 8, 12, 16, 20, 24 and 28.
BCSTo1 outputs the channel control bits for streams BSTo1, 5, 9, 13, 17, 21, 25 and 29.
BCSTo2 outputs the channel control bits for streams BSTo2, 6, 10, 14, 18, 22, 26 and 30.
BCSTo3 outputs the channel control bits for streams BSTo3, 7, 11, 15, 19, 23, 27 and 31.
(3) With stream BSTo4 selected to operate at a data-rate of 2.048Mb/s, the value of the Channel
Control Bit for Channel 0 will be transmitted during the C16o clock period nos. 2040, 2048, 8, 16, 24,
32, 40 and 48.
(4) With stream BSTo8 operated at a data-rate of 8.192Mb/s, the value of the Channel Control Bit for
Channel 1 will be transmitted during the C16o clock period nos. 9 and 17.
Backplane High Impedance Control
BORS Set LOW, Non-32Mb/s Mode.
Setting BORS to a HIGH state will configure the output streams, BSTo0-31, of the
BCSTo Allocation of Channel Control Bits to the Output Streams (non-32Mb/s Mode)
Preliminary Information
.