MT90870 Zarlink Semiconductor, Inc., MT90870 Datasheet - Page 54

• Manufacturer Part Number: MT90870
• Description: Flexible 12k Digital Switch (F12kDX)
• Manufacturer: Zarlink Semiconductor, Inc.

MT90870
13.9
Address 00A3h to 00C2h
Thirty-two Backplane Output Advancement Registers (BOAR0 to BOAR3) allow users to program the output
advancement for output data streams BSTo0 to BSTo31. For 2Mb/s, 4Mb/s, 8Mb/s and 16Mb/s stream
operation the possible adjustment is -2, -4 or -6 cycles of the internal system clock (131.072MHz). For 32Mb/ s
stream operation the possible adjustment is -1, -2 or -3 cycles of the internal system clock (131.072MHz). The
BOAR0 to BOAR3 registers are configured as follows:
13.9.1
The binary value of these two bits is the amount of offset that a particular stream output can be advanced.
When the advancement is 0, the serial output stream has the normal alignment with the Backplane frame
pulse.
54
mode, n = 0 to 15 for 32Mb/s mode)
(where n = 0 to 31 for non-32Mb/s
Backplane Output Advancement For
2Mb/s, 4Mb/s, 8Mb/s & 16Mb/s
clock Rate 131.072 MHz
BOARn Bit
Backplane Output Advancement Registers (BOAR0 - 31)
Backplane Output Advancement Bits 1-0 (BOA1-BOA0)
15-2
1:0
Table 30 - Backplane Output Advancement (BOAR) Programming Table
0 (Default)
-4 cycles
-6 cycles
-2 cycle
Table 29 - Backplane Output Advancement Register (BOAR) Bits
Reserved
BOA(1:0)
Name
Advancement For 32Mb/s
clock Rate 131.072 MHz
Reset
0
0
Backplane Output
0 (Default)
-1 cycle
-2 cycle
-3 cycle
Reserved
Backplane Output Advancement Register
Description
Preliminary Information
Advancement Bits
BOA1
Corresponding
0
0
1
1
BOA0
0
1
0
1