MT90870 Zarlink Semiconductor, Inc., MT90870 Datasheet - Page 41

• Manufacturer Part Number: MT90870
• Description: Flexible 12k Digital Switch (F12kDX)
• Manufacturer: Zarlink Semiconductor, Inc.

Preliminary Information
13.0
This section describes the registers that are used in the device.
13.1
Address 0000h.
The control register defines which memory is to be accessed. It initiates the memory block programming mode
and selects the Backplane data rate mode. The Control Register (CR) is configured as follows:
15-9
2-0
Bit
8
7
6
5
4
3
Reserved
MODE32
C8IPOL
MS(2:0)
COPOL
Name
FPW
MBP
OSB
Detailed Register Description
Control Register (CR)
Reset
0
0
0
0
0
0
0
0
Reserved.
Frame Pulse Width
When LOW, an input frame pulse width of 122ns shall be applied to FP8i. When
HIGH, an input frame pulse width of 244ns shall be applied to FP8i.
32MHz Mode
When LOW, Backplane streams (BSTi0-31 and BSTo0-31) may be individually
programmed for data-rates of 2, 4, 8, or 16Mb/s. When HIGH, the Backplane
streams (BSTi0-15 and BSTo0-15) operate in 32Mb/s mode.
8MHz Input Clock Polarity
The frame boundary is aligned to the clock falling or rising edge. When set LOW,
the frame boundary is aligned to the clock falling edge. When set HIGH, the frame
boundary is aligned to the clock rising edge.
Output Clock Polarity
When set LOW, the output clock is the same polarity as the input clock. When set
HIGH, the output clock is inverted. This applies to both 8MHz (C8o)and 16MHz
(C16o) output clocks.
Memory Block Programming
When LOW, the memory block programming mode is disabled. When HIGH, the
connection memory block programming mode is ready to program the Local
Connection Memory (LCM), and the Backplane Connection Memory (BCM).
Output Stand By
This bit enables the BSTo0 - 31 and the LSTo0 - 15 serial outputs.
When set LOW, the BSTo0-31 and LSTo0-15 are driven high or high impedance,
dependent on the BORS and LORS pin settings respectively, and BCSTo0-3 and
LCSTo0-1 are driven low.
When set HIGH, the BSTo0-31, LSTo0-15, BCSTo0-3 and LCSTo0-1 are enabled.
Memory Select Bits.
These three bits select the connection or data memory for subsequent micro-port
memory access operations:
000, Local Connection Memory (LCM) is selected for Read or Write operations.
001, Backplane Connection Memory (BCM) is selected for Read or Write
operations. 010, Local Data Memory is selected for Read-only operation. 011,
Backplane Data Memory is selected for Read-only operation.
Table 16 - Control Register Bits
ODE Pin
0
1
1
Output Control with ODE pin and OSB bit
OSB bit
X
0
1
Description
BSTo0 - 31, LSTo0 - 15
Disable
Disable
Enable
MT90870
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