MT90870 Zarlink Semiconductor, Inc., MT90870 Datasheet - Page 33

• Manufacturer Part Number: MT90870
• Description: Flexible 12k Digital Switch (F12kDX)
• Manufacturer: Zarlink Semiconductor, Inc.

Preliminary Information
7.0
The MT90870 supports non-multiplexed Motorola microprocessors. The microprocessor port consists of 16-bit
parallel data bus (D0-15), 15-bit address bus (A0-14) and four control signals (CS, DS, R/W and DTA). The data
bus provides access to the internal registers, the Backplane Connection and Data memories, and the Local
Connection and Data memories. Each Backplane memory has 8,192 locations and each Local memory has
4,096 locations. See Table 8, Address Map for Data and Connection Memory Locations (A14=1), for the
address mapping.
Each Connection Memory can be read or written via the 16-bit microprocessor port. The Data Memories can
only be read (but not written) from the microprocessor port.
To prevent the bus ’hanging’ in the event of the MT90870 not receiving a master clock, the microprocessor
port shall complete the DTA handshake when accessed but any data read from the bus will be invalid.
8.0
8.1
The recommended power-up sequence is for the VDD_IO supply (nominally +3.3V) to be established before
the power-up of the VDD_PLL and VDD_CORE supplies (nominally +1.8V). The VDD_PLL and VDD_CORE
supplies may be powered up simultaneously, but neither should 'lead' the VDD_IO supply by more than 0.3V.
All supplies may be powered-down simultaneously.
8.2
Upon power up, the MT90870 should be initialized by applying the following sequence:
8.3
The RESET pin is used to reset the device. When set LOW, an asynchronous reset is applied to the MT90870.
It is synchronized to the internal clock and remains active for 50us following release (set HIGH) of the external
RESET to allow time for the PLL to fully settle. During the reset period, depending on the state of input pins
LORS and BORS, the output streams LSTo0-15 and BSTo0-31 are set to high or high impedance, and all
internal registers and counters are reset to the default state.
The RESET pin must remain low for two input clock cycles (C8i) to guarantee a synchronized reset release.
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Microprocessor Port
Device Power-up, Initialization and Reset
Power-Up Sequence
Initialization
Reset
Set ODE pin to LOW. This configures the LCSTo0-1 output signals to LOW (i.e. to set
optional external output buffers to high impedance), and sets the LSTo0-15 outputs to high
or high impedance, dependent on the LORS input value, and sets the BCSTo0-3 output
signals to LOW (i.e. to set optional external output buffers to high impedance), and sets the
BSTo0-31 outputs to high or high impedance, dependent on BORS input value. Refer to
Pin Description for details of the LORS and BORS pins.
Reset the device by pulsing the RESET pin to zero for at least two cycles of the input
clock, C8i.
Use the Block Programming Mode to initialize the Local and the Backplane Connection
Memories. Refer to Section 6.3, Connection Memory Block Programming.
Set ODE pin to HIGH after the connection memories are programmed to ensure that bus
contention will not occur at the serial stream outputs.
Ensure the TRST pin is permenantly LOW to disable the JTAG TAP controller.
MT90870
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