MT90870 Zarlink Semiconductor, Inc., MT90870 Datasheet - Page 20

• Manufacturer Part Number: MT90870
• Description: Flexible 12k Digital Switch (F12kDX)
• Manufacturer: Zarlink Semiconductor, Inc.

MT90870
4.0
4.1
The input pin, LORS, selects whether the Local output streams, LSTo0-15 are set to high impedance at the
output of the MT90870 itself, or are always driven (active HIGH or active LOW) and a high impedance state, if
required on a per-channel basis, is invoked through an external interface circuit controlled by the LCSTo0-1
signals. Setting LORS to a LOW state will configure the output streams, LSTo0-15, to transmit bi-state
channel data with per-channel high-impedance determined by external circuits under the control of the
LCSTo0-1 outputs.
MT90870 to invoke a high-impedance output on a per-channel basis.
The LORS pin is an asynchronous input and is expected to be hard-wired for a particular system application,
although it may be driven under logic control if preferred.
4.1.1
The data (channel control bit) transmitted by LCSTo0-1 replicates the Local Output Enable Bit (LE) of the
Local Connection Memory, with a LOW state indicating the channel be set to High Impedance. Section 12.3,
Local Connection Memory Bit Definition, refers.
The LCSTo0-1 outputs transmit serial data (channel control bits) at 16.384Mb/s, with each bit representing the
per-channel high impedence state for specific streams. Eight output streams are allocated to each control line
as follows:
(See also Pin Description)
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•
The Channel Control Bit location, within a frame period, for each channel of the Local output streams is
presented in Table 2, LCSTo Allocation of Channel Control Bits to the Output Streams.
As an aid to the description, the channel control bit for a single channel on specific streams is presented, with
reference to Table 2:
(1) The Channel Control Bit corresponding to Stream 0, Channel 0, LSTo0_Ch0, is transmitted on LCSTo0 and
is advanced, relative to the Frame Boundary, by 10 periods of C16o.
(2) The Channel Control Bit corresponding to Stream 14, Channel 0, LSTo14_Ch0, is transmitted on LCSTo0
in advance of the Frame Boundary by three periods of output clock, C16o. Similarly, the Channel Control Bit
for LSTo15_Ch0, is advanced relative to the Frame Boundary by three periods of C16o, on LCSTo1.
The LCSTo0-1 outputs data at a constant data-rate of 16.384Mb/s, independent of the data-rate selected for
the individual output streams, LSTo0-15. Streams at data-rates lower than 16.384Mb/s will have the value of
the respective channel control bit repeated for the duration of the channel. The bit will be repeated twice for
8.192Mb/s streams, four times for 4.096Mb/s streams and eight times for 2.048Mb/s streams. The channel
control bit is not repeated for 16.384Mb/s streams.
Examples are presented, with reference to Table 2:
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LCSTo0 outputs the channel control bits for streams: LSTo0, 2, 4, 6, 8, 10, 12, and 14.
LCSTo1 outputs the channel control bits for streams: LSTo1, 3, 5, 7, 9, 11, 13, and 15.
(3) With stream LSTo4 selected to operate at a data-rate of 2.048Mb/s, the value of the Channel
Control Bit for Channel 0 will be transmitted during the C16o clock period nos. 2040, 2048, 8, 16, 24,
32, 40 and 48.
(4) With stream LSTo8 operated at a data-rate of 8.192Mb/s, the value of the Channel Control Bit for
Channel 1 will be transmitted during the C16o clock period nos. 9 and 17.
Port High Impedance Control
Local Port High Impedance Control
LORS Set LOW
Setting LORS to a HIGH state will configure the output streams, LSTo0-15, of the
Preliminary Information