si4330 Silicon Laboratories, si4330 Datasheet - Page 101

• Manufacturer Part Number: si4330
• Description: Si4330 Ism Receiver
• Manufacturer: Silicon Laboratories

Register 2Eh. Slicer Peak Holder
Register 30h. Data Access Control
Reset value = 00101110
Reset value = 10001101
Name
Name
Type
Type
Bit
Bit
6:4
3:0
1:0
Bit
Bit
7
7
6
5
4
3
2
Reserved
attack[2:0]
decay[3:0]
enpacrx
Reserved
Reserved
Reserved
crcdonly
enpacrx
crc[1:0]
R/W
R/W
Name
Name
lsbfrst
D7
D7
encrc
Reserved.
Attack.
Decay.
Enable Packet RX Handling.
If FIFO Mode (dtmod = 10) is being used automatic packet handling may be enabled.
Setting enpacrx = 1 will enable automatic packet handling in the RX path. Register
30–4D allow for various configurations of the packet structure. Setting enpacrx = 0 will
not do any packet handling in the RX path. It will only receive everything after the sync
word and fill up the RX FIFO.
LSB First Enable.
The LSB of the data will be received first if this bit is set.
CRC Data Only Enable.
When this bit is set to 1 the CRC is checked against the packet data fields only.
Reserved.
Reserved.
CRC Enable.
Cyclic Redundancy Check generation is enabled if this bit is set.
CRC Polynomial Selection.
00:
01:
10:
11:
lsbfrst
R/W
D6
D6
CCITT
CRC-16 (IBM)
IEC-16
Biacheva
attack[2:0]
crcdonly
R/W
R/W
D5
D5
Preliminary Rev 0.2
Reserved
R/W
D4
D4
Reserved
Function
Function
R/W
D3
D3
encrc
R/W
D2
D2
decay[3:0]
R/W
D1
D1
crc[1:0]
Si4330
R/W
D0
D0
101