si4330 Silicon Laboratories, si4330 Datasheet - Page 72

• Manufacturer Part Number: si4330
• Description: Si4330 Ism Receiver
• Manufacturer: Silicon Laboratories

Register 03h. Interrupt/Status 1
Si4330
Reset value = xxxxxxxx
When any of the Interrupt/Status 1 bits change state from 0 to 1 the device will notify the microcontroller by setting
the nIRQ pin LOW if it is enabled in the Interrupt Enable 1 register. The nIRQ pin will go to HIGH and all the
enabled interrupt bits will be cleared when the microcontroller reads this address. If any of these bits is not enabled
in the Interrupt Enable 1 register then it becomes a status signal that can be read anytime in the same location and
will not be cleared by reading the register.
72
Name
Type
Bit
6:5
Bit
7
4
3
2
1
0
Reserved
Reserved
icrcerror
irxffafull
ipkvalid
ifferr
Name
D7
R
ifferr
iext
Reserved
FIFO Underflow/Overflow Error.
When set to 1 the RX FIFO has overflowed or underflowed.
Reserved.
RX FIFO Almost Full. When set to 1 the RX FIFO has met its almost full threshold and
needs to be read by the microcontroller.
External Interrupt.
When set to 1 an interrupt occurred on one of the GPIO’s if it is programmed so. The sta-
tus can be checked in register 0Eh. See GPIOx Configuration section for the details.
Reserved.
Valid Packet Received. When set to 1 a valid packet has been received.
CRC Error.
When set to 1 the cyclic redundancy check is failed.
D6
R
Reserved
D5
R
Preliminary Rev 0.2
irxffafull
D4
R
Function
iext
D3
R
Reserved
D2
R
ipkvalid
D1
R
icrerror
D0
R