si4330 Silicon Laboratories, si4330 Datasheet - Page 69

• Manufacturer Part Number: si4330
• Description: Si4330 Ism Receiver
• Manufacturer: Silicon Laboratories

4C-4E
6B-6F
Add
5C
5D
41
42
43
44
45
46
47
48
49
4A
4B
4F
50
51
53
54
55
56
57
58
59
5A
5B
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
70
71
72
73
74
75
76
77
78
79
7A
7B
7E
7F
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
RC Oscillator Coarse Calibration/Override
Turn Around and 15.4 Length Compliance
Invalid Preamble Threshold and PA Misc
Chargepump Current Trimming/Override
RC Oscillator Fine Calibration/Override
Frequency Hopping Channel Select
Channel Filter Coefficient Address
Channel Filter Coefficient Value
Crystal Oscillator / Control Test
Frequency Hopping Step Size
Nominal Carrier Frequency 1
Nominal Carrier Frequency 0
Modulation Mode Control 1
Modulation Mode Control 2
VCO Calibration / Override
Deltasigma ADC Tuning 1
Deltasigma ADC Tuning 2
Divider Current Trimming
Received Packet Length
Block Enable Override 1
Block Enable Override 2
Block Enable Override 3
Frequency Band Select
VCO Current Trimming
Miscellaneous Settings
LDO Control Override
Frequency Deviation
Received Header 3
Received Header 2
Received Header 1
Received Header 0
Frequency Offset 1
Frequency Offset 2
Calibration Control
LDO Level Setting
Chargepump Test
Header Enable 3
Header Enable 2
Header Enable 1
Header Enable 0
RX FIFO Control
Synthesizer Test
Check Header 1
Check Header 0
Analog Test Bus
AGC Override 1
AGC Override 2
Function/Desc
Digital Test Bus
PLL Tune Time
ADC8 Control
FIFO Access
Modem Test
Table 27. Register Descriptions (Continued)
vcocalov/vcdone
15.4 Length
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
agcovpm
chhd[15]
hden[31]
hden[23]
hden[15]
rxplen[7]
Reserved
cpcurr[1]
rxhd[31]
rxhd[23]
rxhd[15]
chhd[7]
hden[7]
bcrfbyp
pwst[2]
rxhd[7]
enspor
trclk[1]
fhch[7]
fifod[7]
pllts[4]
enfrdv
dsmdt
enmix
adcrst
pfdrst
rccov
enovr
fc[15]
fhs[7]
ends
rcfov
fd[7]
fo[7]
fc[7]
D7
xtalstarthalf
vcocorrov
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
vcocal[6]
chhd[14]
hden[30]
hden[22]
hden[14]
rxplen[6]
ensctest
fbdiv_rst
cpcurr[0]
enrefdac
rxhd[30]
rxhd[22]
rxhd[14]
agcslow
Preliminary Rev 0.2
vcotype
chhd[6]
hden[6]
slicfbyp
endv31
rxhd[6]
fbdivhc
pwst[1]
pllts[3]
enbias
trclk[0]
fhch[6]
fifod[6]
enldet
enxtal
enlna
rcc[6]
sbsel
fc[14]
fhs[6]
rcf[6]
fd[6]
fo[6]
fc[6]
D6
inv_pre_th[3] inv_pre_th[2] inv_pre_th[1] inv_pre_th[0] Ido_pa_boost
Reserved
adccaldone
Reserved
lnacomp[3]
cpforceup
vcocorr[3]
Reserved
Reserved
chfilval[5]
Reserved
Reserved
Reserved
Reserved
Reserved
envcoldo
chhd[13]
hden[29]
hden[21]
hden[13]
rxplen[5]
cpcorrov
d3trim[1]
vcocal[5]
dtmod[1]
rxafthr[5]
rxhd[29]
rxhd[21]
rxhd[13]
enoloop
chhd[5]
hden[5]
adc8[5]
pwst[0]
rxhd[5]
enmx3
fhch[5]
fifod[5]
pllts[2]
dttype
enpga
endv2
enadc
agcen
dtb[5]
rcc[5]
hbsel
fc[13]
fhs[5]
rcf[5]
ents
fd[5]
fo[5]
fc[5]
D5
adctuneovr
lnacomp[2]
enphpwdn
cpforcedn
vcocorr[2]
Reserved
chfilval[4]
Reserved
Reserved
Reserved
oscdeten
chhd[12]
hden[28]
hden[20]
hden[12]
rxplen[4]
cpcorr[4]
d3trim[0]
vcocal[4]
endv1p5
dtmod[0]
rxafthr[4]
rxhd[28]
rxhd[20]
rxhd[12]
enrcfcal
chhd[4]
hden[4]
adc8[4]
lnagain
rxhd[4]
dsmod
clkhyst
enifldo
enrc32
envcm
fhch[4]
fifod[4]
pllts[1]
atb[4]
dtb[4]
enbf4
rcc[4]
fc[12]
fhs[4]
enpa
rcf[4]
fd[4]
fo[4]
fb[4]
fc[4]
D4
Data
Alt_PA_Seq
lnacomp[1]
adctune[3]
dsorder[1]
chfiladd[3]
vcocorr[1]
Reserved
Reserved
Reserved
dvbshunt
chfilval[3]
adcoloop
hden[27]
hden[19]
cpcorr[3]
d2trim[1]
vcocal[3]
enbias2x
rxafthr[3]
chhd[11]
hden[11]
rxplen[3]
manppol
rxhd[27]
rxhd[19]
rxhd[11]
hden[3]
cdconly
chhd[3]
adc8[3]
rxhd[3]
enrfldo
fhch[3]
fifod[3]
pllts[0]
OOkth
atb[3]
dtb[3]
enbf5
enbf3
rcc[3]
fhs[3]
eninv
fc[11]
rccal
rcf[3]
pga3
fd[3]
fo[3]
fb[3]
fc[3]
D3
turn_around
lnacomp[0]
dsorder[0]
chfiladd[2]
adctune[2]
vcocorr[0]
enmaninv
chfilval[2]
Reserved
cdccur[2]
enamp2x
chhd[10]
hden[26]
hden[18]
hden[10]
rxplen[2]
vcocaldp
cpcorr[2]
d2trim[0]
vcocal[2]
adcref[2]
rxafthr[2]
rxhd[10]
refclksel
rxhd[26]
rxhd[18]
enpllldo
rcosc[2]
chhd[2]
hden[2]
adc8[2]
endv32
diglvl[2]
rxhd[2]
pllt0[2]
enbf11
fhch[2]
fifod[2]
envco
atb[2]
dtb[2]
rcc[2]
fc[10]
fhs[2]
rcf[2]
pga2
fd[8]
fd[2]
fo[2]
fb[2]
fc[2]
_en
D2
d1p5trim[1]
adctune[1]
chfiladd[1]
modtyp[1]
dsrstmod
chfilval[1]
enmanch
hden[25]
hden[17]
cdccur[1]
vcocur[1]
vcocal[1]
Phase[1]
rxafthr[1]
rxplen[1]
cpcorr[1]
endigldo
adcref[1]
rxhd[25]
rxhd[17]
refclkinv
pgath[1]
hden[9]
hden[1]
diglvl[1]
rcosc[1]
chhd[9]
chhd[1]
adc8[1]
rxhd[9]
rxhd[1]
enbf12
fhch[1]
fifod[1]
pllt0[1]
vcocal
bufovr
atb[1]
dtb[1]
enbf2
rcc[1]
fhs[1]
encp
rcf[1]
pga1
fd[1]
fo[1]
fo[9]
fb[1]
fc[1]
fc[9]
Si4330
D1
d1p5trim[0]
endigpwdn
adctune[0]
chfiladd[0]
modtyp[0]
pa_vbias_
chfilval[0]
cdccur[0]
vcocur[0]
vcocal[0]
Phase[0]
rxafthr[0]
hden[24]
hden[16]
rxplen[0]
cpcorr[0]
adcref[0]
rxhd[24]
rxhd[16]
pgath[0]
diglvl[0]
enwhite
rcosc[0]
chhd[8]
chhd[0]
hden[8]
hden[0]
adc8[0]
skipvco
distogg
pllreset
rxhd[8]
rxhd[0]
enmx2
pllt0[0]
fhch[0]
fifod[0]
atb[0]
dtb[0]
enbuf
rcc[0]
fhs[0]
boost
dsrst
enbg
rcf[0]
pga0
fd[0]
fo[0]
fo[8]
fb[0]
fc[8]
fc[0]
D0
69
Default
POR
FFh
FFh
FFh
FFh
0Eh
1Dh
1Dh
0Ch
BBh
00h
00h
00h
00h
00h
52h
14h
44h
00h
00h
80h
40h
03h
00h
00h
40h
00h
00h
00h
24h
00h
00h
81h
02h
03h
20h
00h
20h
00h
00h
75h
80h
09h
00h
00h
09h
37h
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