si4330 Silicon Laboratories, si4330 Datasheet - Page 117

• Manufacturer Part Number: si4330
• Description: Si4330 Ism Receiver
• Manufacturer: Silicon Laboratories

Register 53h. PLL Tune Time
The total settling time (cold start) of the PLL after the calibration can be calculated as T
Reset value = 01010010
Reset value = 01010100
Invalid preamble will be evaluated during this period: (invalid_preamble_Threshold x 4) x Bit Rate period.
Register 54h. PA Boost
Name
Name
Type
Type
Bit
7:3
2:0
7:6
5:2
Bit
Bit
Bit
1
0
pa_vbias_boost PA VBIAS Boost.
inv_pre_th[5:2] Invalid Preamble Threshold.
Reserved[7:6]
ldo_pa_boost
pllts[4:0]
Name
D7
D7
pllt0
Name
Reserved[7:6]
R/W
PLL Soft Settling Time (T
This register will set the settling time for the PLL from a previous locked frequency in
Tune mode. The value is configurable between 0 µs and 310 µs, in 10 µs intervals. The
default plltime corresponds to 100 µs. See formula above.
PLL Settling Time (T
This register will set the time allowed for PLL settling after the calibrations are completed.
The value is configurable between 0 µs and 70 µs, in 10 µs steps. The default pllt0 corre-
sponds to 20 µs. See formula above.
D6
D6
Reserved.
LDO PA Boost.
pllts[4:0]
D5
R/W
D5
O
Preliminary Rev 0.2
).
D4
S
).
D4
inv_pre_th
R/W
D3
Function
Function
D3
D2
D2
ldo_pa_boost pa_vbias_boost
CS
R/W
D1
= T
R/W
pllt0
D1
S
+ T
O
Si4330
.
R/W
D0
D0
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