si4330 Silicon Laboratories, si4330 Datasheet - Page 73

• Manufacturer Part Number: si4330
• Description: Si4330 Ism Receiver
• Manufacturer: Silicon Laboratories

Bit
6:5
Bit
6:5
7
4
3
2
1
0
7
4
3
2
1
0
Table 29. When are Individual Status Bits Set/Cleared if not Enabled as Interrupts?
Reserved Reserved.
Reserved Reserved.
icrcerror
irxffafull
ipkvalid
Status
Reserved
Reserved
Name
icrcerror
irxffafull
ipkvalid
ifferr
Status
iext
Name
ifferr
iext
Set if there is a FIFO overflow or underflow. Cleared by applying FIFO reset.
Set when the number of bytes in the RX FIFO is greater than the Almost Full threshold.
Cleared when the number of bytes in the RX FIFO is below the Almost Full threshold.
External interrupt source.
Set up the successful reception of a packet (no RX abort). Cleared upon receiving and
acknowledging the Sync Word for the next packet.
Set if the CRC computed from the RX packet differs from the CRC in the TX packet. Cleared
at the start of reception for the next packet.
Set if there is a FIFO Overflow or Underflow. It is cleared only by applying FIFO reset to
the specific FIFO that caused the condition.
Reserved.
Will be set when the number of bytes received (and not yet read-out) in RX FIFO is greater
than the Almost Full threshold set by SPI. It is automatically cleared when we read enough
data from RX FIFO so that the number of data bytes not yet read is below the Almost Full
threshold.
External interrupt source
Reserved.
Goes high once a packet is fully received (no RX abort). It is automatically cleaned once
we receive and acknowledge the Sync Word for the next packet.
Goes High once the CRC computed during RX differs from the CRC sent in the packet by
the TX. It is cleaned once we start receiving new data in the next packet.
Table 28. Interrupt or Status 1 Bit Set/Clear Description
Preliminary Rev 0.2
Set/Clear Conditions
Set/Clear Conditions
Si4330
73