si4330 Silicon Laboratories, si4330 Datasheet - Page 31

• Manufacturer Part Number: si4330
• Description: Si4330 Ism Receiver
• Manufacturer: Silicon Laboratories

Si4330
The Invalid Preamble Detector issues an interrupt when no valid preamble signal is found. After the receiver is
enabled, the Invalid Preamble Detector output is ignored for 16 Tb (Where Tb is the time of a bit duration) to allow
the receiver to settle. The Invalid Preamble Detect interrupt can be used to save power and speed-up search in
receive mode. It is advised to mask the invalid preamble interrupt when Antenna Diversity is enabled.
The Received Signal Strength Indicator (RSSI) provides a measure of the signal strength received on the tuned
channel. The resolution of the RSSI is 0.5 dB. This high resolution RSSI enables accurate channel power
measurements for clear channel assessment (CCA), and carrier sense (CS) functionality.
Frequency mistuning caused by crystal inaccuracies can be compensated by enabling the digital Automatic
Frequency Control (AFC) in receive mode.
TM
A comprehensive programmable Packet Handler including key features of Silicon Labs’ EZMac
is integrated to
create a variety of communication topologies ranging from peer-to-peer networks to mesh networks. The extensive
programmability of the packet header allows for advanced packet filtering which in turn enables a mix of broadcast,
group, and point-to-point communication.
A wireless communication channel can be corrupted by noise and interference, and it is therefore important to
know if the received data is free of errors. A cyclic redundancy check (CRC) is used to detect the presence of
erroneous bits in each packet. A CRC is computed and appended at the tail of each transmitted packet and verified
by the receiver to confirm that no errors have occurred. The Packet Handler and CRC are extremely valuable
features which can significantly reduce the load on the system microcontroller allowing for a simpler and cheaper
microcontroller.
5.6. Synthesizer
An integrated Sigma Delta (ΣΔ) Fractional-N PLL synthesizer capable of operating from 240–960 MHz is provided
on-chip. Using a ΣΔ synthesizer has many advantages; it provides large amounts of flexibility in choosing data rate,
deviation, channel frequency, and channel spacing.
The PLL and - modulator scheme is designed to support any desired frequency and channel spacing in the
range from 240–960 MHz with a frequency resolution of 156.25 Hz (Low band) or 312.5 Hz (High band).
Selectable
Fref = 10 M
PFD
CP
LPF
RX
Divider
VCO
N
Figure 10. PLL Synthesizer Block Diagram
The reference frequency to the PLL is 10 MHz. The PLL utilizes a differential L-C VCO, with integrated on-chip
spiral inductors. The output of the VCO is followed by a configurable divider which will divide down the signal to the
desired output frequency band. The modulus of this divider stage is controlled dynamically by the output from the
- modulator. The tuning resolution of the - modulator is determined largely by the over-sampling rate and the
number of bits carried internally. The tuning resolution is sufficient to tune to the commanded frequency with a
maximum accuracy of 312.5 Hz anywhere in the range between 240–960 MHz.
5.6.1. VCO
The output of the VCO is automatically divided down to the correct output frequency depending on the hbsel and
fb[4:0] fields in "Register 75h. Frequency Band Select". A 2X VCO is utilized to help avoid problems due to
frequency pulling, especially when turning on the integrated Power Amplifier. In receive mode, the LO frequency is
automatically shifted downwards (without reprogramming) by the IF frequency of 937.5 kHz, allowing receive
Preliminary Rev 0.2
31