mt46h32m16lf Micron Semiconductor Products, mt46h32m16lf Datasheet - Page 48

• Manufacturer Part Number: mt46h32m16lf
• Description: 512mb X16, X32 Mobile Ddr Sdram
• Manufacturer: Micron Semiconductor Products

Figure 12:
Bank/Row Activation
PDF: 09005aef82ce3074/Source: 09005aef82ce20c9
ddr_mobile_sdram_cmd_op_timing_dia_fr3.08__3.fm - Rev. D 05/08 EN
S12
0
1
S10 S9
0
0
0
0
1
1
1
1
S15 S14
0
0
0
0
1
1
1
1
Device Type
LPDDR2
LPDDR
Reserved
0
0
1
1
0
0
1
1
Status Register Definition
31..16
DQ31..DQ16
S31..S16
0
0
1
1
0
0
1
1
S8
0
1
0
1
0
1
0
1
Notes:
S13
0
1
0
1
0
1
0
1
1
Refresh Multiplier
Reserved
0.25X
Reserved
Reserved
2X
1X
Reserved
Reserved
15
Density
512Mb
DQ15
128Mb
256Mb
1Gb
Reserved
Reserved
S15
Reserved
Reserved
Density
1. Reserved bits should be set to zero (0) for future compatibility.
2. Refresh multiplier is based on the memory device’s on-board temperature sensor. Required
Before any READ or WRITE commands can be issued to a bank within the Mobile DDR
SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE
command, which selects both the bank and the row to be activated, as shown in
Figure 9. After a row is opened with an ACTIVE command, a READ or WRITE command
may be issued to that row, subject to the
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been “closed” (precharged). The minimum time
interval between successive ACTIVE commands to the same bank is defined by
14
DQ14
S14
S11
0
1
average periodic refresh interval =
DQ13
13
S13
Device Width
32 bits
16 bits
Type
12
DQ12
S12
2
Width
DQ11
11
S11
Refresh Rate
S7
...
0
X
DQ10
10
S10
S6
...
0
X
DQ9
9
S9
S5
...
0
X
DQ8
8
S8
S4
...
0
X
DQ7
7
S7
48
Revision ID
Revision ID
The manufacturer’s revision number starts at ‘0000’
and increments by ‘0001’ each time a change in the
specification (AC timings or feature set), IBIS (pull-
up or pull-down characteristics), or process occurs.
DQ6
6
S6
t
REFI × multiplier.
DQ5
5
S5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
S3
DQ4
4
RCD specification.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
S4
Manufacturer ID
DQ3
S2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
S3
3
S1
DQ2
2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S2
S0
DQ1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
S1
Reserved
Infineon
Elpida
Reserved
Reserved
Reserved
Reserved
Winbond
ESMT
NVM
Reserved
Reserved
Reserved
Reserved
Micron
DQ0
Manufacturer ID
Samsung
0
S0
I/O bus (CLK L->H edge)
Mobile DDR SDRAM
©2007 Micron Technology, Inc. All rights reserved
Status register
Operations
t
RC.