ics9248-172 ETC-unknow, ics9248-172 Datasheet - Page 12

• Manufacturer Part Number: ics9248-172
• Description: Single Chip, System Clock Piii/1651 Chipset 147mhz; Sdram Clocks
• Manufacturer: ETC-unknow

Advance Information
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-172 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
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PCI_STOP# Timing Diagram
ICS9248-172
PCI_STOP# is an asynchronous input to the ICS9248-172. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS9248-172 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width
guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
inside the ICS9248-172.
(Free-running)
CPU_STOP#
PCI_STOP#
PCICLK_F
PCICLK_F
CPUCLK
(Internal)
(Internal)
PCICLK
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