ics9248-172 ETC-unknow, ics9248-172 Datasheet - Page 14

• Manufacturer Part Number: ics9248-172
• Description: Single Chip, System Clock Piii/1651 Chipset 147mhz; Sdram Clocks
• Manufacturer: ETC-unknow

Advance Information
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9248-172. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is
100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped
in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than
4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
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ICS9248-172
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
3. All other clocks continue to run undisturbed.
to the CPU clocks inside the ICS9248-172.
PCI_STOP# (High)
CPU_STOP#
INTERNAL
PD# (High)
CPUCLK
CPUCLK
PCICLK
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