ics9248-171 ETC-unknow, ics9248-171 Datasheet - Page 10

• Manufacturer Part Number: ics9248-171
• Description: Single Chip, System Clock K7/1647 Chipset 147mhz; Sdram Clocks
• Manufacturer: ETC-unknow

Advance Information
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
Notes:
1.
2.
3.
4.
5.
6.
Third party brands and names are the property of their respective owners.
ICS9248-171
through byte 6
The ICS clock generator is a slave/receiver, I
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
Dummy Command Code
Dummy Byte Count
Controlle r (Host)
Address
Start Bit
Stop Bit
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
D2
(H )
How to Write:
For more information, contact ICS for an I
The information in this section assumes familiarity with I
General I
ICS (Sla ve/Re ceiver)
A CK
A CK
A CK
A CK
A CK
A CK
A CK
A CK
A CK
A CK
A CK
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
2
C serial interface information
(H)
2
C component. It can read back the data stored in the latches for
10
2
C programming application note.
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• ICS clock sends first byte (Byte 0) through byte 7
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
Controlle r (Host)
Address
Start Bit
Stop Bit
2
D3
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
C programming.
(H )
How to Read:
ICS (Slave/Rece ive r)
Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
A CK
(H)