ics9248-171 ETC-unknow, ics9248-171 Datasheet - Page 2

• Manufacturer Part Number: ics9248-171
• Description: Single Chip, System Clock K7/1647 Chipset 147mhz; Sdram Clocks
• Manufacturer: ETC-unknow

Advance Information
Notes:
1:
2:
3:
Third party brands and names are the property of their respective owners.
ICS9248-171
Pin Descriptions
25, 26, 30, 31, 32,
33, 36, 37, 38, 39,
20, 19, 15, 14, 13
3, 11, 16, 23, 29,
PIN NUMBER
8, 17, 28, 35, 40
to program logic Hi to VDD or GND for logic low.
34, 41, 48
Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
Internal pull-down resistor of 120K to GND.
Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
45, 47
42, 43
10
12
18
21
22
24
27
44
46
1
2
4
5
6
7
9
CPUCLKT (1:0)
DG_STOP#
PCI_STOP#
(12:11, 9:0 )
CPUCLKC0
PIN NAME
PCICLK_F
SDRAM 10
(5:4) (2:0)
PCICLK3
M ODE
AVDD48
SDRAM
PCICLK
SDATA
AVDD
48MHz
FS0
FS1
FS2
FS3
AGP0
AGP1
SCLK
REF0
PD#
GND
VDD
X1
X2
2, 3
2, 3
1, 3
2, 3
1
1, 3
1
1
TYPE
PWR
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I/O
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
DG_STOP halts SDRAM and/or AGP clocks at logic "0" when driven low.
The stops selection can be programed through I
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
Crystal input,nominally 14.318M Hz.
Crystal output, nominally 14.318MHz.
Ground pins
Power supply pins, nominal 3.3V
Analog power supply pin, nominal 3.3V
Frequency select pin.
14.318 M Hz reference clock.
Frequency select pin.
AGP outputs defined as 2X PCI. These may not be stopped.
AGP outputs defined as 2X PCI. These may not be stopped.
Free running PCICLK not stoped by PCI_STOP#
Frequency select pin.
PCI clock outputs.
PCI clock output.
Function select pin, 1=Desktop M ode, 0=M obile M ode.
Analog power supply pin, nominal 3.3V
Frequency select pin.
48MHz output clock
Clock input of I
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level,
when input low
SDRAM clock output.
SDRAM clock outputs.
Data pin for I
"True" clocks of differential pair CPU outputs. These open drain outputs
need an external 1.5V pull-up.
"Complementory" clocks of differential pair CPU outputs. This open drain
output need an external 1.5V pull-up.
2
2
C circuitry 5V tolerant
2
C input, 5V tolerant input
DESCRIPTION
2
C.