ics9248-64 ETC-unknow, ics9248-64 Datasheet
ics9248-64
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ics9248-64 Summary of contents
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... AMD-K7 System Clock Chip TM General Description The ICS9248- main clock synthesizer chip for AMD- K7 based systems. This provides all clocks required for such a system when used with a Zero Delay Buffer Chip such as the ICS9179-06. Spread Spectrum may be enabled by driving the SPREAD# pin active ...
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... V; Inputs with pull-up resistors max cap loads; Select @ 66MHz max cap loads; Select @ 100MHz CL = max cap loads; Select @ 133MHz Logic Inputs X1 & X2 pins From target Freq 50 50% 6 ICS9248-64 +0 MIN TYP MAX -0.3 0 2.0 ...
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... 0 1 Note 2 0.4 Note 2 0.2 Note 3 550 required for switching, where /2-150mV; Max=(Vpullup (external) 7 ICS9248-64 MIN TYP MAX UNITS 2.4 2.8 0.32 0.4 -27 - 2 400 1000 260 500 TYP MAX 50 1.2 0.175 0.4 21 0.85 0.9 V pullup(external ...
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... Volts (unless otherwise stated) L CONDITIONS 1.5 Volts T 8 ICS9248-64 MIN TYP MAX UNITS 2.6 3.1 V 0.17 0.4 V - 470 500 ps 120 500 ps MIN TYP MAX UNITS 2 ...
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... L CONDITIONS 1.5 Volts T 9 ICS9248-64 MIN TYP MAX UNITS 0.31 0.4 V - 290 500 ps MIN TYP MAX UNITS ...
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... ACK ACK ACK ACK ACK 2 C component. It can read back the data stored in the latches for 2 C interface, the protocol is set to use only "Block-Writes" from the controller. The 10 ICS9248- programming. How to Read: ICS (Slave/Receiver) Start Bit Address D3 (H) ACK Byte Count ...
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... The programming resistors should be located close to the series termination resistor to minimize the current loop area more important to locate the series termination resistor close to the driver than the programming resistor. Via to VDD 2K 8.2K Clock trace to load Series Term. Res. Fig ICS9248-64 ...
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... Crystal Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-64 device shown, the outputs Stop Low on the next falling edge after PD# goes low asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. ...
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... CPU_STOP asychronous input to the clock synthesizer used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS9248-64. All other clocks will continue to run while the CPUCLKs clocks are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse ...
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... PCI_STOP# Timing Diagram PCI_STOP asynchronous input to the ICS9248-64 used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-64 internally. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock ...
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... ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to 15 obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9248-64 In Inches COMMON DIMENSIONS MIN MAX ...