stlc5465 STMicroelectronics, stlc5465 Datasheet - Page 11

• Manufacturer Part Number: stlc5465
• Description: Multi Hdlc With Switching Matrix Associated
• Manufacturer: STMicroelectronics

I - PIN INFORMATION (continued)
I.2 - Pin Description (continued)
Type : I1 = Input TTL ;
MICROPROCESSOR INTERFACE (continued)
Pin N°
51
52
53
54
55
56
57
63
64
65
66
67
68
69
70
71
72
75
76
77
78
79
80
81
82
83
84
85
86
87
88
91
92
93
94
95
96
97
98
99
O4 = Output CMOS 4mA ;
O8D = Output CMOS 8mA, Open Drain ;
O8T = Output CMOS 8mA, Tristate
NDSACK0/NDTACK
SIZE1/NBHE/NUDS
NDSACK1/READY
SIZE0/NLDS
A20/ADM15
A21/ADM16
A22/ADM17
A23/ADM18
R/W / NWR
NDS/NRD
A10/AD10
A11/AD11
A12/AD12
A13/AD13
A14/AD14
A15/AD15
NAS/ALE
Symbol
A0/AD0
A1/AD1
A2/AD2
A3/AD3
A4/AD4
A5/AD5
A6/AD6
A7/AD7
A8/AD8
A9/AD9
A16
A17
A18
A19
DO
D1
D2
D3
D4
D5
D6
D7
D8
Type
O8T
O8T
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I3
I3
I3
I3
I3
I1
I1
I1
I1
I2 = I1 + Pull-up ;
O4T = O4 + Tristate ;
Transfer Size0 (68020)/Lower Data Strobe (68000)
Transfer Size1 (68020)/Bus High Enable (Intel) / Upper Data Strobe (68000)
Data Strobe, Acknowledge and Size0 (68020)/Data Transfer Acknowledge
(68000)
Data Strobe, Acknowledge and Size0 (68020)/Data Transfer Acknowledge
(Intel)
Address Strobe(Motorola) / Addresss Latch Enable(Intel)
Read/Write (Motorola / Write(Intel)
Data Strobe (Motorola 68020); at Vdd for 68000/Read Data (Intel)
Address bit 0 (Motorola 68020); at Vdd for 68000 / Address/Data bit 0 (Intel)
Address bit 1 (Motorola) / Address/Data bit 1 (Intel)
Address bit 2 (Motorola) / Address/Data bit 2 (Intel)
Address bit 3 (Motorola) / Address/Data bit 3 (Intel)
Address bit 4 (Motorola) / Address/Data bit 4 (Intel)
Address bit 5 (Motorola) / Address/Data bit 5 (Intel)
Address bit 6 (Motorola) / Address/Data bit 6 (Intel)
Address bit 7 (Motorola) / Address/Data bit 7 (Intel)
Address bit 8 (Motorola) / Address/Data bit 8 (Intel)
Address bit 9 (Motorola) / Address/Data bit 9 (Intel)
Address bit 10 (Motorola) / Address/Data bit 10 (Intel)
Address bit 11 (Motorola) / Address/Data bit 11 (Intel)
Address bit 12 (Motorola) / Address/Data bit 12 (Intel)
Address bit 13 (Motorola) / Address/Data bit 13 (Intel)
Address bit14 (Motorola) / Address/Data bit 14 (Intel)
Address bit15 (Motorola) / Address/Data bit 15 (Intel)
Address bit16 (Motorola) / Address bit 16 (Intel)
Address bit17 (Motorola) / Address bit 17 (Intel)
Address bit18 (Motorola) / Address bit 18 (Intel)
Address bit19 (Motorola) / Address bit 19 (Intel)
Address bit 20 from P (input) / Address bit 15 for SRAM (output)
Address bit 21 from P (input) / Address bit 16 for SRAM (output)
Address bit 22 from P (input) / Address bit 17 for SRAM (output)
Address bit 23 from P (input) / Address bit 18 for SRAM (output)
Data bit 0 for P if not multiplexed (see Note 1).
Data bit 1 for P if not multiplexed
Data bit 2 for P if not multiplexed
Data bit 3 for P if not multiplexed
Data bit 4 for P if not multiplexed
Data bit 5 for P if not multiplexed
Data bit 6 for P if not multiplexed
Data bit 7 for P if not multiplexed
Data bit 8 for P if not multiplexed
I3 = I1 + Hysteresis ;
O8 = Output CMOS 8mA, "1" and "0" at Low Impedance ;
O8DT = Output CMOS 8mA, Open Drain or Tristate ;
Function
I4 = I3 + Pull-up ;
STLC5465B
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