stlc5465 STMicroelectronics, stlc5465 Datasheet - Page 32

• Manufacturer Part Number: stlc5465
• Description: Multi Hdlc With Switching Matrix Associated
• Manufacturer: STMicroelectronics

STLC5465B
III - FUNCTIONAL DESCRIPTION (continued)
Figure 15: GCI channel to/from ISDN Channel
32/101
in 16 GCI channels.
The contents of B1 and/or B2 can be descram-
bled or not. If descrambled the 32 B1/B2 belong
to GCI channels mandatory.
Receiving six bit word (A, E, S1, S2, S3, S4) from
any 16 “ISDN channels”, TDM side. The 16 “six
bit word” are stored automatically in the external
shared memory.
Transmitting the contents of Monitor and Com-
mand / Indicate channels to 16 GCI channels.
TS3m+2
TS3m+1
TS3m
If TDM at 4 Mb/s
m: ISDN channel
or even timeslot
TDM side
PCM at 2 Mb/s
can be selected
number, 0 to 9
odd timeslot
B1
B1
B1
B1
B1
B1
B1
B1
B1
B2
B2
B2
B2
B2
B2
B2
B2
S1
S2
S3
S4
D
D
A
E
Queue located in
shared memory
Command Indicate controllers
Six bit word
C/I interrupt
DESCRAMBLER
DESCRAMBLER
RX
SCRAMBLER /
SCRAMBLER /
Primitive
Alarm Indication Signal.
This detection concerns 16 hyperchannels. One
hyperchannel comprises 16 bits (B1 and B2 only).
The Alarm Indications for the 16 hyperchannels are
stored automatically in the external shared mem-
ory. See AISD bit of Switching Matrix Configuration
Reg SMCR (0C)H on page 71.
Microprocessor
See SBV bit of General Configuration Register
GCR (02)H on page 68.
TX
GCI side
n: GCI channel
number, 0 to 7
C1
C2
C3
C4
B1
B1
B1
B1
B1
B1
B1
B1
B1
B2
B2
B2
B2
B2
B2
B2
B2
M1
M2
M3
M4
M5
M6
M7
M8
D
D
A
E
TS4n+1
TS4n
TS4n+3
TS4n+2
Monitor controllers
TX
Queue located in
shared memory
MON interrupt
RX