stlc5465 STMicroelectronics, stlc5465 Datasheet - Page 81

• Manufacturer Part Number: stlc5465
• Description: Multi Hdlc With Switching Matrix Associated
• Manufacturer: STMicroelectronics

VIII - INTERNAL REGISTERS (continued)
VIII.13 - HDLC Transmit Command Register - HTCR (18)H
READ : READ COMMAND MEMORY
CH0/4 : These five bits define one of 32 channels.
C1/C0 : COMMAND BITS
P0/1
F
NCRC : CRC NOT TRANSMITTED
CSMA : Carrier Sense Multiple Access with Contention Resolution
bit15
CH4
CH3
: PROTOCOL BITS
: Flag
READ = 1, READ COMMAND MEMORY.
READ = 0, WRITE COMMAND MEMORY.
F = 1 ; flags are transmitted between closing flag of current frame and opening flag of next frame.
F = 0 ; "1" are transmitted between closing flag of current frame and opening flag of next frame.
NCRC = 1, the CRC is not transmitted at the end of the frame.
NCR C =0, the CRC is transmitted at the end of the frame.
CSMA = 1, CB output and the Echo Bit are taken into account during this channel transmission
by the Tx HDLC.
CSMA = 0, CB output and the Echo Bit are defined by V11 (see " Time slot Assigner Data
Register TADR (16)H").
C1
P1
0
0
1
1
0
0
1
1
CH2
C0
P0
0
1
0
1
0
1
0
1
CH1
ABORT ; if this command occurs during the current frame, HDLC Controller transmits seven "1"
immediately, afterwards HDLC Controller transmits "1" or flag in accordance with F bit, generates
an interrupt and waits new command such as START orn CONTINUE.
If this command occurs after transmitting a frame, HDLC Controller generates an interrupt and
waits a new command such as START or CONTINUE.
START ; Tx DMA Controller is now going to transfer first frame from buffer related to initial
descriptor. The initial descriptor address is provided by the Initiate Block located in external
memory.
CONTINUE ; Tx DMA Controller is now going to transfer next frame from buffer related to next
descriptor. The next descriptor address is provided by the previous descriptor from which the
related frame had been already transmitted.
HALT ; after transmitting frame, HDLC Controller transmits "1" or flag in accordance with F bit,
generates an interrupt and is waiting new command such as START or CONTINUE.
HDLC
Transparent Mode 1 (per byte) ; the fill character defined in FCR Register is taken into account.
Transparent Mode 2 (per byte) ; the fill character defined in FCR Register is not taken into account.
Reserved
CH0
READ
Nu
After reset (0000)
bit8
CF
PEN
bit7
Transmission Mode
Commands Bits
CSMA
H
NCRC
F
P1
P0
STLC5465B
C1
81/101
bit 0
C0