stlc5465 STMicroelectronics, stlc5465 Datasheet - Page 94

• Manufacturer Part Number: stlc5465
• Description: Multi Hdlc With Switching Matrix Associated
• Manufacturer: STMicroelectronics

STLC5465B
IX - EXTERNAL REGISTERS (continued)
IX.2 - Receive Descriptor
This receive descriptor is located in shared memory. The quantity of descriptors is limited by the memory
size only.
The 5 first words located in shared memory to RDA+00 from RDA+08 are written by the microprocessor
and read by the DMAC only. The 6th word located in shared memory in RDA+10 is written by the DMAC
only during the frame reception and read by the microprocessor.
SOB
RBA
RDA
NRDA : Next Receive Descriptor Address. LSB of NRDA Low is at Zero mandatory.
NBR
IX.2.1 - Bits written by the Microprocessor only
IBC
EOQ
IX.2.2 - Bits written by the Rx DMAC only
IX.2.3 - Receive Buffer
Each receive buffer is defined by its receive descriptor.
The maximum size of the buffer is 2048 words (1 word=2 bytes)
Note: for Motorola processors, a swap may be necessary to read/write the Receive Buffer.
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RDA+00
RDA+02
RDA+04
RDA+06
RDA+08
RDA+10
FR
1
1
0
0
0
0
0
: Size Of the Buffer associated to descriptor up to 2048 words (1 word = 2 bytes).
: Receive Buffer Address. LSB of RBA Low is at Zero mandatory.
: Receive Descriptor Address.
: Number of Bytes Received (up to 4096).
: Interrupt if the buffer has been completed.
: End Of Queue.
ABT
If SOB = 0, DMAC goes to next descriptor.
IBC=1, the DMAC generates an interrupt if the buffer has been completed.
EOQ=1, the DMAC stops immediately its reception generates an interrupt (HDLC = 1 in IR) and
waits a command from the HRCR (HDLC Receive Command Register).
EOQ=0, the DMAC continues.
0
0
0
0
1
1
1
RBA+SOB-2
FR
15
RBA
OVF
ABT
0
0
0
0
0
1
0
14
FCRC
OVF
IBC
13
0
1
0
0
0
0
1
Not used
Not used
FCRC
EOQ
The frame has been received without error. The end of frame is in this buffer.
The frame has been received with false CRC.
If NBR is different to 0, the buffer related to this descriptor is completed.The end
of frame is not in this buffer.
If NBR is equal to 0, the Rx DMAC is receiving a frame.
ABORT. The received frame has been aborted by the remote transmitter or the
local microprocessor.
OVERFLOW of FIFO. The received frame has been aborted.
The received frame had not an integer of bytes.
12
15
Next Receive Descriptor Address Low (16 bits)
AVAILABLE in the Receive Buffer
SECOND BYTE LOCATION
11
Receive Buffer Address Low (16 bits)
LAST BYTE LOCATION
10
9
Number of Bytes Received (NBR)
8
Size Of the Buffer (SOB)
7
Definition
8
6
7
AVAILABLE in the Receive Buffer
5
NRDA High (8 bits)
LAST - 1 BYTE LOCATION
RBA High (8 bits)
THIRD BYTE LOCATION
FIRST BYTE LOCATION
4
3
2
1
0
0
0