stlc5465 STMicroelectronics, stlc5465 Datasheet - Page 82

• Manufacturer Part Number: stlc5465
• Description: Multi Hdlc With Switching Matrix Associated
• Manufacturer: STMicroelectronics

STLC5465B
VIII - INTERNAL REGISTERS (continued)
PEN
CF
VIII.14 - HDLC Receive Command Register - HRCR (1A)H
READ : READ COMMAND MEMORY
CH0/4 : These five bits define one of 32 channels.
C1/C0 : COMMAND
P0/1
FM
CRC
82/101
bit15
CH4
CH3
: CSMA PENALTY significant if CSMA = 1
: Common flag
: PROTOCOL BITS
: Flag Monitoring.
: CRC stored in external memory
PEN = 1, the penalty value is 1 ; a transmitter which has transmitted a frame correctly will count
(PRI +1) logic one received from Echo pin before transmitting next frame. (PRI, priority class 8
or 10 given by the buffer descriptor related to the frame.
PEN = 0, the penalty value is 2 ; a transmitter which has transmitted a frame correctly will count
(PRI +2) logic one received from Echo pin before transmitting next frame. (PRI, priority class 8
or 10 given by the transmit descriptor related to the frame).
CF = 1, the closing flag of previous frame and opening flag of next frame are identical if the next
frame is ready to be transmitted.
CF = 0, the closing flag of previous frame and opening flag of next frame are distinct.
READ = 1, READ COMMAND MEMORY.
READ = 0, WRITE COMMAND MEMORY.
This bit is a status bit read by the microprocessor.
FM=1: HDLC Controller is receiving a frame or HDLC Controller has just received one flag.
FM is put to 0 by the microprocessor.
CRC = 1, the CRC is stored at the end of the frame in external memory.
CRC = 0, the CRC is not stored into external memory.
C1
P1
0
0
1
1
0
0
1
1
CH2
C0
P0
0
1
0
1
0
1
0
1
CH1
ABORT ; if this command occurs during receiving a current frame, HDLC Controller stops the
reception, generates an interrupt and waits new command such as START orn CONTINUE.
If this command occurs after receiving a frame, HDLC Controller generates an interrupt and waits
a new command such as START or CONTINUE.
START ; Rx DMA Controller is now going to transfer first frame into buffer related to the initial
descriptor. The initial descriptor address is provided by the Initiate Block located in external
memory.
CONTINUE ; Rx DMA Controller is now going to transfer next frame into buffer related to next
descriptor. The next descriptor address is provided by the previous descriptor from which the
related frame had been already received.
HALT ; after receiving frame, HDLC Controller stops the reception, generates an interrupt and
waits a new command such as START or CONTINUE.
HDLC
Transparent Mode 1 (per byte) ; the fill character defined in FCR Register is taken into account.
Transparent Mode 2 (per byte) ; the fill character defined in FCR Register is not taken into account.
Reserved
CH0
READ
AR21
After reset (0000)
AR20
bit8
Transmission Mode
AR11
Commands Bits
bit7
H
AR10
CRC
FM
P1
P0
C1
bit 0
C0