stlc5465 STMicroelectronics, stlc5465 Datasheet - Page 35

• Manufacturer Part Number: stlc5465
• Description: Multi Hdlc With Switching Matrix Associated
• Manufacturer: STMicroelectronics

III.4.2 - Exchange with the shared memory
A Fetch Buffer located in the microprocessor inter-
face allows to reduce the shared memory access
cycle for the microprocessor.
It is used whatever microprocessor selected thanks
to MOD0/2 pins.
This Fetch Buffer consists of one Write FIFO and
four Read Fetch Memories.
III.4.2.1 - Write FIFO
When the microprocessor delivers the address
word named An to write data named [An] in the
shared memory in fact it writes data [An] and
address word An in the Write FIFO (Deep 4 words).
If An is in Fetch Memory, [An] is removed in Fetch
Memory.
The number of wait cycles for the microprocessor
is strongly reduced.
Figure 17.1: Write FIFO and Fetch Memories.
Write FIFO
From microprocessor
To shared memory
An+1, [An+1]
An+2, [An+2]
An+3, [An+3]
An, [An]
microprocessor
Shared memory
Microprocessor
interface
III.4.2.2 - Read Fetch Memory
When the microprocessor delivers the address
word named An to read data named [An] out of the
shared memory in fact it reads data [An] from one
of four Read Fetch Memories.
The number of wait cycle for the microprocessor is
strongly reduced and can reach zero when An,
address word delivered by the microprocessor, and
data [An] is already in the Read Fetch Memory and
validated.
The source of [An] is truly the shared memory
whatever An.
III.4.3 - Definition of the Interface for the differ-
ent microprocessors
The signals connected to the microprocessor inter-
face are presented on the following figures for the
different microprocessor.
Read Fetch
Memory
From shared memory
To microprocessor
Fetch Memories
An, [An]
Four
STLC5465B
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