stlc5465 STMicroelectronics, stlc5465 Datasheet - Page 77

• Manufacturer Part Number: stlc5465
• Description: Multi Hdlc With Switching Matrix Associated
• Manufacturer: STMicroelectronics

VIII - INTERNAL REGISTERS (continued)
SCR
(cont’d)
VIII.9 - Connection Memory Address Register - CMAR (10)H
This 16 bit register is constituted by two registers : DESTINATION REGISTER (DSTR) and ACCESS MODE
REGISTER (AMR) respectively 8 bits and 6 bits.
DESTINATION REGISTER (DSTR)
When DSTR Register is written by the microprocessor, a memory access is launched. DSTR has two use
modes depending on CM (bit of CMAR).
CM = 1, access to connection memory (read or write) ;
OTS 0/4 : Output time slot 0/4 define OTSy with : 0
OM0/2
See table hereafter when DR04, DR24, DR44 and/or DR64 are at “1”; the bits of SMCR define the TDMs
at 4 Mbit/s.
The IM2/1 bits of Source Register (SRCR of CMDR) indicate the DIN pin number and the OM2/1 bits of
Destination Register (DSTR of CMAR) indicate the Dout pin number.
The ITS4/0 and IM0 bits of Source Register (SRCR of CMDR) indicate the input timeslot number. (IM0 bit
is the Least Significant Bit; it indicates either even timeslot or odd timeslot.
bit15
Nu
(bit4)
ITS4
IM2 (bit7)
0
0
0
0
1
: The scrambler is enabled when the output timeslot defined by the destination register (DSTR)
0
0
1
1
Nu
: Output Time Division Multiplex 0/2 define OTDMq with : 0
is an output timeslot belonging to any TDM except the two GCI multiplexes; the contents of this
output timeslot will be scrambled in accordance with the IUT-T V.29 Rec.
The descrambler is enabled when the output timeslot defined by the destination register (DSTR)
is an output timeslot belonging to the two GCI multiplexes except any TDM; the contents of this
output timeslot is descrambled in accordance with the IUT-T V.29 Rec.
Only 32 timeslots of 256 can be scrambled or/and descrambled:
GCI side, only B1 and B2 can be selected in each GCI channel (16 GCI channels are available:
8 per GCI multiplex).
*TDM side, it is forbidden to select a given timeslot more than once when several TDMs are selected.
SCR=0, the scrambler or the descrambler are disabled; the contents of output timeslots are not modified.
ACCESS MODE REGISTER (AMR)
TC
(bit3)
ITS3
0
0
0
0
1
CACL CAC
IM1 (bit6)
0
1
0
1
(bit2)
ITS2
0
0
0
0
1
BID
=
(bit1)
ITS1
DIN pin
CM
DIN0
DIN2
DIN4
DIN6
0
0
0
0
1
After reset (0800)
READ OM2
bit8
(bit0)
ITS0
0
0
1
1
1
bit7
y
OM2 (bit7)
31,
H
OM1
0
0
1
1
DESTINATION REGISTER (DSTR)
(bit5)
IMO
0
1
0
1
1
OM0 OTS4 OTS3 OTS2 OTS1 OTS0
q
OM1(bit6)
7.
0
1
0
1
Input timeslot number
63
0
1
2
3
=
STLC5465B
DOUT pin
DOUT0
DOUT2
DOUT4
DOUT6
77/101
bit 0