stlc5465 STMicroelectronics, stlc5465 Datasheet - Page 72

• Manufacturer Part Number: stlc5465
• Description: Multi Hdlc With Switching Matrix Associated
• Manufacturer: STMicroelectronics

STLC5465B
VIII - INTERNAL REGISTERS (continued)
TS0
TS1
SGV
SAV
SGC
ME
AISD
DR04 : Data Rate of TDM0 is at 4Mb/s. Case:M1=M0=0
DR24 : Data Rate of TDM2 is at 4Mb/s.Case:M1=M0=0
DR44 : Data Rate of TDM4 is at 4Mb/s.Case: M1=M0=0
72/101
: Tristate 0
: Tristate 1
: Pseudo Random Sequence Generator Validated
: Pseudo Random Sequence analyzer Validated
: Pseudo Random Sequence Generator Corrupted
: MESSAGE ENABLE
: Alarm Indication Signal Detection.
TS0 = 1, the DOUT0/3 and DOUT6/7 pins are tristate : "0" is at low impedance, "1" is at low
impedance and the third state is high impedance.
TS0 = 0, the DOUT0/3 and DOUT6/7 pins are open drain : "0" is at low impedance, "1" is at high
impedance.
TS1 = 1, the DOUT4/5 pins are tristate : "0" is at low impedance, "1" is at low impedance and
the third state is high impedance.
TS1 = 0, the DOUT4/5 pins are open drain : "0" is at low impedance, "1" is at high impedance.
SGV = 1,PRS Generator is validated.The Pseudo Random Sequence is transmitted during the
related time slot(s).
SGV = 0, PRS Generator is reset."0" are transmitted during the related time slot.
SAV = 1, PRS analyzer is validated.
SAV = 0, PRS analyzer is reset.
When SGC bit goes from 0 to 1, one bit of sequence transmitted is corrupted.
When the corrupted bit has been transmitted, SGC bit goes from 1 to 0 automatically.
ME = 1 The contents of Connection Memory is output on DOUT0/7 continuously.
ME = 0 The contents of Connection Memory acts as an address for the Data Memory.
AISD = 1, the Alarm Indication Signal detection is validated.
Sixteen independent detections are performed for sixteen hyperchannels. The contents of any
input hyperchannel (B1, B2, D) switched (in transparent mode or not) on GCI channels is
analysed independently.
For each GCI channel, the 16bits of B1 and B2 are checked together; when all “one” has been
detected during 30 milliseconds, a status is stored in the Command/ Indicate interrupt queue
and an interrupt is generated if not masked (like the reception of primitive from GCI multiplexes).
See “RECEIVE Command/Indicate INTERRUPT” on page 97.
AISD=0, the Alarm Indication Signal detection for 16 hyperchannels is not validated.
DR04 = 1, the signal received from DIN0 pin and the signal delivered by Dout0 pin are at 4Mb/s.
DIN1 pin and DOUT1 pin are ignored.
The Time Division Multiplex 0 is constituted by 64 timeslots numbered from 0 to 63.
DR04 = 0, the signals received from DIN0/1 pins and the signals delivered by Dout0/1 pins are
at 2Mb/s.
R24 = 1, the signal received from DIN2 pin and the signal delivered by Dout2 pin are at 4Mb/s.
DIN3 pin and DOUT3 pin are ignored.
The Time Division Multiplex 2 is constituted by 64 timeslots numbered from 0 to 63.
DR24 = 0, the signals received from DIN2/3 pins and the signals delivered by Dout2/3 pins are
at 2Mb/s.
DR44 = 1, the signal received from DIN4 pin and the signal delivered by Dout4 pin are at 4Mb/s.
DIN5 pin and DOUT5 pin are ignored.
TDM4/5 cannot be GCI multiplexes.
The Time Division Multiplex 4 is constituted by 64 timeslots numbered from 0 to 63.
DR44 = 0, the signals received from DIN4/5 pins and the signals delivered by Dout4/5 pins are
at 2Mb/s.