pnx1500 NXP Semiconductors, pnx1500 Datasheet - Page 254

• Manufacturer Part Number: pnx1500
• Description: Pnx15xx Series Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
Table 8: Registers Description
PNX15XX_SER_3
Product data sheet
Bit
Offset 0x04 0820
31:0
Offset 0x04 0824
31:0
Offset 0x04 0828
31:0
Offset 0x04 082C
This register controls the type of access to XIO and provides status.
31:10
9
8
7
6
5
4
3:0
Offset 0x04 0830
31:22
21:16
15:8
7:0
Symbol
gpxio_addr
gpxio_wdata
gpxio_rdata
Reserved
gpxio_cyc_pending
gpxio_done
clr_gpxio_done
gpxio_init
Reserved
gpxio_rd
gpxio_ben
Reserved
nand_ctrls
command_b
command_a
GPXIO_address
GPXIO_write_data
GPXIO_read_data
GPXIO_ctrl
NAND-Flash controls
Acces
s
R/W
R/W
R
R
R
R
W
R/W
R
R/W
R/W
R/W
R/W
R/W
Value
0
0
0
0
0
0
0
0
0
0
0
17
0
0
Rev. 3 — 17 March 2006
Description
General Purpose XIO cycle address. This register sets the address
for an indirect read or write to/from XIO address space. Only 4 byte
writes are allowed in this register. The values programmed for bits 0
and 1 are not used by the XIO module. Refer to gpxio_ben.
General Purpose XIO cycle data. This register is programmed with
data for a write cycle.
General Purpose XIO cycle data. This register contains the data of
a read cycle after completion.
1 = GPXIO transaction on XIO is pending.
0 = GPXIO has completed or not yet started.
General Purpose XIO cycle complete. This bit is cleared by writing 1
to bit 6 or 7. It will also be cleared by writing to the GPXIO interrupt
clear register.
1 = Clear “gpxio_done.”
1 = Initiate a transaction on XIO. The type of transaction will match
the profile of the selected aperture. This bit gets cleared if the cycle
has been initiated. This bit clears bit 8 if set.
1 = Read command on XIO
0 = Write command on XIO
Active low byte enables to be used on the indirect XIO cycle. These
are used to determine how many bytes to access and the lower two
address bits for use in “gpxio_addr”.
This field controls the type of NAND-Flash access cycle. The bits
are defined as follows:
[21]: 1= 64-MB device support; 0 = 32 MB and smaller device
support
[20]: 1 = Include data in access cycle; 0 access does not include
data phase(s)
[19:18] = No. of commands to be used in NAND-Flash access
[17:16] = No. of address phases to be used in NAND-Flash access.
For 64-MB devices, 11 provide four address phases and 10 provide
three address phases.
This is the second command for NAND-Flash when two commands
are required to complete a cycle.
This is the command type to be used with NAND-Flash cycles when
one or more commands are required to complete a cycle.
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Chapter 7: PCI-XIO Module
PNX15xx Series
7-35