pnx1500 NXP Semiconductors, pnx1500 Datasheet - Page 665

• Manufacturer Part Number: pnx1500
• Description: Pnx15xx Series Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
Table 10: VLD Registers
PNX15XX_SER_3
Product data sheet
Bit
31:28
27:24
23:20
19:16
15:14
13
12:7
6
5
4
3:2
1:0
Offset 0x07 5010
31:16
15:7
6
5
4
3
Symbol
Vertical back. rsize
Horizontal back. rsize
Vertical for. rsize
Horizontal for. rsize
Reserved
mpeg2mode
Reserved
mv_concealment
intra_vlc
frame_prediction_frame
_dct
picture_structure
picture_type
Reserved
Reserved
RL overflow
DMA RL output done
DMA Header output
done
DMA input done
…Continued
VLD_MC_STATUS
Acces
s
R/W
R/W
R/W
R/W
R
R/W
R
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
NI
NI
NI
NI
NI
NI
NI
NI
NI
NI
0
0
0
0
Value
Rev. 3 — 17 March 2006
Chapter 21: MPEG-1 and MPEG-2 Variable Length Decoder
Description
Number of bits per backward vertical motion vector that are residual
in the picture.
Number of bits per backward horizontal motion vector that are
residual in the picture.
Number of bits per forward vertical motion vector that are residual in
the picture.
Number of bits per forward horizontal motion vector that are residual
in the picture.
1 = indicates if the current sequence is MPEG-2
0 = indicates if the current sequence is MPEG-1 (for error checking
only)
1 = indicates forward motion vectors are coded in all intra
macroblock headers of a picture.
0 = indicates forward motion vectors are not coded in all intra
macroblock headers of a picture.
Use DCT table zero (intra_vlc = “0”)or one (intra_vlc = “1”)
If 1, motion_type = FRAME, and dct_type = 0.
If 0, motion_type and dct_type follow the decoded values in the
mb_header from the VLD. CPU should set it to 0 for Field Pictures
and 1 for MPEG-1.
1=top-field
2=bottom-field
3=frame picture
0=reserved.
1=I
2=P
3=B
0=D (MPEG-1 only)
Logic ‘1’ indicates Overflow of run/level values with in a block. Refer
to
procedure. This bit is cleared by writing a logic ‘1’ to it.
Logic ‘1’ indicates that the Run Length data FIFO has been written
to main memory. This bit is cleared by writing a logic ‘1’ to it.
Logic ‘1’ indicates that the Run Length data FIFO has been written
to main memory. This bit is cleared by writing a logic ‘1’ to it.
Conditions for setting this bit depends on the value of the
DMA_Input_Done field in the VLD_CTL register. Refer to
VLD Control
This bit is cleared by writing a logic ‘1’ to it.
Section 3.4 Error Handling
and
Section 3.3.1
for details on the error handling
for details.
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
Table 3
21-17