pnx1500 NXP Semiconductors, pnx1500 Datasheet - Page 749

• Manufacturer Part Number: pnx1500
• Description: Pnx15xx Series Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
The controller’s state diagram
and “Update” of data and instructions in order to leave the contents of a data register
or an instruction register undisturbed until serial scan in is finished and the Update
state is entered. By separating the Shift and Update states, the contents of a register
(the parallel stage) is not affected during scan in/out.
The TAP controller must be in Test Logic Reset state after power up. It remains in that
state as long as TMS is held at 1. The controller transitions to Run-Test/Idle state
from Test Logic Reset state when TMS = 0. The Run-Test/Idle state is an idle state of
the controller in between scanning in/out an instruction/data register. The “Run-Test”
part of the name refers to start of built-in tests. The “Idle” part of the name refers to all
other cases. Note that there are two similar substructures in the state diagram, one
for scanning in an instruction and another for scanning in data. To scan in/out a data
register, one has to scan in an instruction first.
An instruction or data register must have at least two stages, the shift register stage
and the parallel input/output stage. When an n-bit data register is to be “read,” the
register is selected by an instruction. The register’s contents are “captured” first
Figure 1:
0
1
Test Logic
Reset
Run-Test/
Idle
State Diagram of TAP Controller
0
Rev. 3 — 17 March 2006
1
(Figure
1
0
Select
DR Scan
Capture
DR
Shift
Exit1
DR
Pause
DR
Exit2
DR
Update
DR
DR
1
1) shows separate states for “Capture,” “Shift”
0
0
1
1
1
0
0
1
1
0
0
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Chapter 24: TM3260 Debug
PNX15xx Series
1
0
Select
IR Scan
Capture
IR
Shift
IR
Exit1
IR
Pause
IR
Exit2
IR
Update
IR
1
0
0
1
1
1
0
0
1
1
0
0
24-3