pnx1500 NXP Semiconductors, pnx1500 Datasheet - Page 316

• Manufacturer Part Number: pnx1500
• Description: Pnx15xx Series Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
Figure 1:
Figure 2:
DMA
CPU
The two MTL Ports of the DDR SDRAM Controller
Arbitration in the DDR Controller
2.1.3 Observing Start State
2.2.1 The First Level of Arbitration: Between the DMA and the CPU
2.2 Arbitration
DDR controller, once configured, executes an exit of self-refresh mode which starts
back on the DDR devices. There is no boot scripts provision for this mode, therefore
an external eeprom is required to activate this mode.
The START and WARM_START fields of MMIO register IP_2031_CTL will be set to
‘0’ when the respective start action has completed. Do not perform a start action
while the DDR controller is still busy performing a previous start action.
The DDR SDRAM Controller provides an arbiter between the DMA traffic (generated
by the PNX15xx Series modules) and the TM3260 CPU as pictured in
page
The DDR SDRAM Controller arbiter is responsible for scheduling between MTL
transaction requests from the different MTL ports. The arbitration scheme has been
optimized to achieve a high DDR bandwidth efficiency (at the cost of DDR latency).
The arbitration flow is pictured in
9-3.
MTL port 0
MTL port 1
CPUs out of budget
do second level
DMA arbitration
in HRT window
Rev. 3 — 17 March 2006
begin
OR
end
Figure
arbitration
CPU wins
2.
DDR command
request queue
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Chapter 9: DDR Controller
PNX15xx Series
Section 1 on
9-3